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Introduction to Intel’s 32nm Process Technology

White Paper: Intel has been in high volume manufacturing on 32nm process technology with 2nd generation high-k + metal gate transistors since 2009.

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Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met

Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

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Presentation: Low Power Optimize a 32nm SoC Platform Technology

Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

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RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC App

Brief examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Role of High-K Gate Dielectrics

Presentation Discusses Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices.

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High Performance 32nm Logic Technology

Record NMOS and PMOS drive currents are reported, along with the tightest contacted gate pitch for a 32nm or 28nm technology.

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