Mark Bohr Intel Senior Fellow Kaizad Mistry 22 nm Program Manager May, 2011 1 Key Messages • Intel is introducing revolutionary Tri-Gate transistors on its 22 nm logic technology • Tri-Gate transistors provide an unprecedented combination of improved performance and energy efficiency • 22 nm processors using Tri-Gate transistors, code-named Ivy Bridge, are now demonstrated working in systems • Intel is on track for 22 nm production in 2H ‘11, maintaining a 2-year cadence for introducing new technology generations • This technological breakthrough is the result of Intel’s highly coordinated research-development-manufacturing pipeline • Tri-Gate transistors are an important innovation needed to continue Moore’s Law 2 Intel Technology Roadmap Process Name Lithography st 1 Production P1266 45 nm 2007 P1268 32 nm 2009 P1270 22 nm 2011 P1272 14 nm 2013 P1274 10 nm 2015 Intel continues our cadence of introducing a new technology generation every two years 3 Traditional Planar Transistor Gate High-k Dielectric Oxide Source Drain Silicon Substrate Traditional 2-D planar transistors form a conducting channel in the silicon region under the gate electrode when in the “on” state 4 22 nm Tri-Gate Transistor Gate Drain Oxide Source Silicon Substrate 3-D Tri-Gate transistors form conducting channels on three sides of a vertical fin structure, providing “fully depleted” operation Transistors have now entered the third dimension! 5 22 nm Tri-Gate Transistor Gate Oxide Silicon Substrate Tri-Gate transistors can have multiple fins connected together to increase total drive strength for higher performance 6 22 nm Tri-Gate Transistor Gate Oxide Silicon Substrate Tri-Gate transistors can have multiple fins connected together to increase total drive strength for higher performance 7 22 nm Tri-Gate Transistor Gates Fins 8 32 nm Planar Transistors 22 nm Tri-Gate Transistors 9 Intel Transistor Leadership 2003 90 nm 2005 65 nm 2007 45 nm 2009 32 nm 2011 22 nm SiGe SiGe Invented SiGe Strained Silicon nd 2 Gen. SiGe Strained Silicon Invented Gate-Last High-k Metal Gate nd 2 Gen. Gate-Last High-k Metal Gate Strained Silicon High-k Metal Gate First to Implement Tri-Gate Tri-Gate 10 Std vs. Fully Depleted Transistors Bulk Transistor Gate Oxide Source Gate Inversion Layer Drain Depletion Region Silicon Substrate Silicon substrate voltage exerts some electrical influence on the inversion layer (where source-drain current flows) The influence of substrate voltage degrades electrical sub-threshold slope (transistor turn-off characteristics) NOT fully depleted 11 Std vs. Fully Depleted Transistors Partially Depleted SOI (PDSOI) Gate Source Floating Body Drain Oxide Silicon Substrate Floating body voltage exerts some electrical influence on the inversion layer, degrading sub-threshold slope NOT fully depleted Not used by Intel 12 Std vs. Fully Depleted Transistors Fully Depleted SOI (FDSOI) Source Gate Oxide Drain Extremely thin silicon layer Silicon Substrate Floating body eliminated and sub-threshold slope improved Requires expensive extremely-thin SOI wafer, which adds ~10% to total process cost Not used by Intel 13 Std vs. Fully Depleted Transistors Fully Depleted Tri-Gate Transistor Gate Oxide Silicon Fin Silicon Substrate Gate electrode controls silicon fin from three sides providing improved sub-threshold slope Inversion layer area increased for higher drive current Process cost adder is only 2-3% 14 Transistor Operation Channel Current Read the full Intel’s Revolutionary 22 nm Transistor Technology.