Manual do dispositivo Cyclone® IV, Volume 1, Capítulo 5: Redes de clock e PLLs

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Cyclone® IV FPGAs Support Cyclone® IV FPGAs Support Cyclone® IV FPGAs Support

653862
2012-09-30
Public

Descrição

Descreve as redes de clock hierárquicas e os loops de bloqueio de fase (PLLs). Reconfigure a frequência do clock do contador PLL e a mudança de fase em tempo real e ajuste dinamicamente a mudança de fase do clock de saída.

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