Manual do dispositivo Cyclone® IV, Volume 2: transceptores

Fazer download

Cyclone® IV FPGAs Support Cyclone® IV FPGAs Support Cyclone® IV FPGAs Support

654346
2015-02-05
Public

Descrição

Manual do dispositivo Cyclone® IV, Volume 2: transceptores

Instruções de uso

Ativos relacionados
Título e descrição
Format
Idioma
Ação
Describes the cyclical redundancy check (CRC) error detection feature in user mode and how to recover from soft errors.
Exibir
This chapter provides features and details on how LEs work, how LABs contain groups of LEs, and how LABs interface with the other blocks in Cyclone® IV devices.
Exibir
Describes and provides examples about the different modes to dynamically reconfigure different portions of the transceivers without powering down any part of the device.
Exibir
Describes the memory interface pin support and the external memory interface. Cyclone® IV devices can easily interface with a broad range of external memory devices, including DDR2 SDRAM, DDR SDRAM, and QDR II SRAM.
Exibir
Describes the hierarchical clock networks and phase locked loops (PLLs). Reconfigure the PLL counter clock frequency and phase shift in real time and dynamically adjust the output clock phase shift.
Exibir
Describes the configuration and remote system upgrades using volatile SRAM cells to store configuration data.
Exibir
Cyclone® IV Device Handbook, Volume 3: Device Datasheet
Exibir
Describes information about external power supply requirements, hot socketing specifications, power-on reset (POR) requirements, and their implementation in Cyclone® IV devices.
Exibir
Describes the boundary-scan test (BST) features that support IEEE Std. 1149.1 and IEEE Std. 1149.6. The IEEE Std. 1149.6 (AC JTAG) is only supported on the high-speed serial interface (HSSI) transceivers in Cyclone® IV GX devices.
Exibir
Built on an optimized low-power process, the Cyclone® IV device family offers lowest power, high functionality with the lowest cost with 3.125 Gbps transceivers
Exibir
Describes the electrical and switching characteristics including operating conditions, power consumption, transceiver specifications, transceiver core, and periphery performance.
Exibir
Embedded memory structure consists of columns of M9K memory blocks configured to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers.
Exibir
A combination of on chip resources and external interfaces that help increase performance, reduce system cost, and lower the power consumption of digital signal processing (DSP) systems.
Exibir
Describes the I/O and high speed I/O capabilities driven by the diversification of I/O standards in many low cost applications, and the significant increase in required I/O performance.
Exibir
This chapter discusses Cyclone® IV GX transceivers and supported protocols.
Exibir
Multiple reset signals control the transceiver channels independently. Individual reset signals for each channel instantiated and one power-down signal for each transceiver block.
Exibir
Cyclone® IV Device Handbook, Volume 1: Device Core, I/O Interfaces, and System Integration
Exibir