The PHY Interface for the PCI Express* (PCIe*), SATA, and USB Architectures (PIPE) is intended to enable the development of functionally equivalent PCIe*, SATA, and USB PHY’s. Such PHY’s can be delivered as discrete IC’s or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions, which must be incorporated in a PIPE compliant PHY, and it defines a standard ...interface between such a PHY and a media access layer controller (MAC) and link layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the PCI Express* base specification, SATA 3.0 specification, or USB 3.1 specification rather than repeating its content. In case of conflicts, the PCIe* Base specification, SATA 3.0 specification, and USB 3.1 specification shall supersede the PIPE spec.