Stratix® IV FPGA

Think high logic utilization and short compile times. Large FPGA designs require efficient design methodology and tool support. Intel® Quartus® Prime development software enables the highest Stratix® IV FPGA performance and productivity by incorporating the highest logic utilization and the shortest compile times in the industry.

• The Stratix® IV GX FPGA is fully compliant with PCI-SIG* for PCI Express* (PCIe*) Gen1 and Gen2 (x1, x4, and x8) and is on the PCI-SIG* integrators list.
• The Stratix® IV GT FPGA is the only FPGA with integrated 11.3 Gbps transceivers.
• Highest density with up to 820K logic elements (LEs), 23.1 Mb of embedded memory, and up to 1,288 18 x 18 multipliers.
• Highest FPGA performance with a 2 speed grade advantage and the industry's most advanced logic and routing architecture.
• Unprecedented system bandwidth with up to 48 high-speed transceivers at up to 8.5 Gbps, or up to 24 transceivers at up to 11.3 Gbps. These transceivers are optimized for 100G applications and 1,067 Mbps (533 MHz) DDR3 memory interfaces.
• Lowest power with up to 50 percent lower power than any other high-end FPGA in the market enabled by 40 nm benefits and Programmable Power Technology.
• Hardened intellectual property (IP) for PCI Express* Gen1 (2.5 Gbps) and Gen2 (5.0 Gbps) with up to four x8 blocks delivering a full endpoint or root-port function.
• Superior signal integrity with the ability to drive a 50" backplane at 6.375 Gbps with Plug & Play Signal Integrity.

DSP

Without compromising the performance required for compute-intensive applications, Stratix® IV DSP blocks provide low power, low cost, and small footprint programmable processing solution. Both Stratix® IV GX, Stratix® IV GT, and Stratix® IV E family variants provide a DSP- and memory-rich, highly parallel alternative to digital signal processors. Stratix® IV GX FPGAs add additional transceivers for high-speed connectivity and support for protocols such as the Serial RapidIO* standard and CPRI/OBSAI.

Intel also provides the tools necessary to implement your DSP algorithm through the use of the DSP Builder for Intel® FPGAs and Platform Designer tools, both part of the Intel® Quartus® development software performance and productivity-enhancing design software that supports Stratix® IV FPGAs. With the 8.0 release of the DSP Builder for Intel FPGAs tool, Intel added a number of new Simulink* blocksets (the Advanced Blockset library) that vastly improve your productivity in the synthesis of multichannel designs.

Embedded Processing

Nios® II embedded processors version extend the embedded software capabilities of Intel's 40 nm FPGAs. This allows you to add a memory management or memory protection unit to your Nios II designs for operating system support and software protection. With Nios II embedded processors, you can add dozens of 300 MIPS processors in a single high-density device. You can accelerate time-critical software subroutines automatically by converting ANSI C code into hardware accelerators with the Nios II C-to-Hardware (C2H) acceleration compiler. You can add hardware accelerators to boost system performance and/or reduce system power consumption. See what’s new in the latest release.

Memory Interfaces

Faster, more robust, simpler, and lower power—Intel’s external memory solutions support high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks. The smart interface module is a hardened I/O module with programmable input and output delays for lane de-skew, dynamically calibrated on-chip termination (OCT), and controllable drive strength and slew rate. It offers the unique ability to swap between parallel or serial termination on-the-fly between read and write operations and saves 1.2 W power for a typical design.

ASIC Prototyping

Stratix® IV FPGAs are 40 nm FPGAs, making them the ideal choice for use in ASIC prototyping platforms when you are performing verification of your next ASIC or ASSP design.