• Select the Intel^® Quartus^® Prime Pro Edition if you are beginning a new Intel^® Arria^® 10, Intel^® Cyclone^® 10 GX, Intel^® Stratix^® 10 or Intel^® Agilex™ design, or to take advantage of the unique features of Intel^® Quartus^® Prime Pro Edition.
  Figure 2. Intel Quartus Prime Feature Support Matrix
• Select the Intel^® Quartus^® Prime Standard Edition software if your design must target Arria^® V, Arria^® , Intel^® Cyclone^® 10 LP, Cyclone IV, Cyclone V, or MAX^® series devices, and you do not want to migrate you design to a device that Intel^® Quartus^® Prime Pro Edition supports.
• Intel^® Quartus^® Prime Pro Edition software does not support the following Intel^® Quartus^® Prime Standard Edition features:
  • I/O Timing Analysis
  • NativeLink third party tool integration (other third-party tool integration available)
  • Video and Image Processing Suite IP Cores
  • Talkback features
  • Various register merging and duplication settings
  • Saving a node-level netlist as .vqm

Project Tasks Pane

The Tasks pane (View > Tasks) provides one-click launch of common project tasks, such as creating design files, specifying project settings, running compilation, debug and timing closure, and device programming.

The Project Navigator

• Suppress Message—suppresses all messages that match the exact text you specify.
• Suppress Messages with Matching ID—suppresses all messages that match the message ID number you specify, ignoring variables.
• Suppress Messages with Matching Keyword—suppresses all messages that match the keyword or hierarchy you specify.
• Message Suppression Manager—allows you to create and edit message suppression rules. You can define message suppression rules by message text, message ID number, or keyword.

To disable or enable automatic sending of problem reports, follow these steps:

1. Click Tools > Options.
2. Click the Internet Connectivity tab.
3. Under Problem report, turn on or off Always send report to Intel when internal error occurs (command-line only).
   Figure 10. Problem Report Option

Manual Design Partition Export

Follow these steps to manually export a design partition with the Export Design Partition dialog box:

1. Open a project and create one or more design partitions. Creating a Design Partition describes this process.
2. Run synthesis (Processing > Start > Start Analysis & Synthesis) or full compilation (Processing > Start Compilation), depending on which compilation results that you want to export.
3. Click Project > Export Design Partition, and specify one or more options in the Export Design Partition dialog box:
   Figure 24. Export Design Partition Dialog Box
   • Select the Partition name and the compilation Snapshot for export.
   • To include any entity-bound .sdc files in the exported .qdb, turn on Include entity-bound SDC files for the selected partition.
4. Click OK. The compilation results for the design partition exports to the file that you specify.

The Quartus Database Viewer can display the following attributes of a .qdb file:

• Use appropriate case for your platform in file path references.
• Use a character set common to both platforms.
• Do not change the forward‑slash (/) and back‑slash (\) path separators in the .qsf. The Intel^® Quartus^® Prime software automatically changes all back‑slash (\) path separators to forward‑slashes (/ )in the .qsf.
• Observe the target platform’s file name length limit.
• Use underscore instead of spaces in file and directory names.
• Change library absolute path references to relative paths in the .qsf.
• Ensure that any external project library exists in the new platform’s file system.
• Specify file and directory paths as relative to the project directory. For example, for a project titled foo_design, specify the source files as: top.v, foo_folder /foo1.v, foo_folder /foo2.v, and foo_folder/bar_folder/bar1.vhdl.
• Ensure that all the subdirectories are in the same hierarchical structure and relative path as in the original platform.

Figure 29. All Inclusive Project Directory Structure

For example, in the directory structure shown you can specify top.v as ../source/top.v and foo1.v as ../source/foo_folder/foo1.v.

Figure 30.  Intel^® Quartus^® Prime Project Directory Separate from Design Files

1. The project directory takes precedence over the project libraries.
2. For Linux, the Intel^® Quartus^® Prime software creates the file in the altera.quartus directory under the <home> directory.
3. All library files are relative to the libraries. For example, if you specify the user_lib1 directory as a project library and you want to add the /user_lib1/foo1.v file to the library, you can specify the foo1.v file in the .qsf as foo1.v. The Intel^® Quartus^® Prime software includes files in specified libraries.
4. If the directory is outside of the project directory, an absolute path is created by default. Change the absolute path to a relative path before migration.
5. When copying projects that include libraries, you must either copy your project library files along with the project directory or ensure that your project library files exist in the target platform.
   • On Windows*, the Intel^® Quartus^® Prime software searches for the quartus2.ini file in the following directories and order:
   • USERPROFILE, for example, C:\Documents and Settings\<user name>
   • Directory specified by the TMP environmental variable
   • Directory specified by the TEMP environmental variable
   • Root directory, for example, C:\

• Logic design files (.v, .vdh, .bdf, .edf, .vqm)
• Timing constraint files (.sdc)
• Quartus project settings and constraints (.qdf, .qpf, .qsf)
• IP files (.ip, .v, .sv, .vhd, .qip, .sip, .qsys)
• Platform Designer-generated files (.qsys, .ip, .sip)
• EDA tool files (.vo, .vho )

Generate or modify these files manually if you use a scripted design flow. If you use an external source code control system, check-in project files anytime you modify assignments and settings.

create_revision Command

create_revision defines the properties of a new project revision.

create_revision <name> -based_on <revision_name> -set_current -new_rev_type \
     <rev_type> -root_partition_qdb_file <root qdb>

get_project_revisions Command

get_project_revisions returns a list of all revisions in the project.

get_project_revisions <project_name>

delete_revision Command

delete_revision deletes the revision you specify from your project.

delete_revision <revision name>

set_current_revision Command

set_current_revision sets the revision you specify as the current revision.

set_current_revision -force <revision name>

project_archive Command

project_archive archives your project into a single, compressed .qar file.

project_archive <name>.qar

restore_archive Command

Restores an archived project to a destination directory with optional overwriting of current contents.

project_restore <name>.qar -destination <directory name> -overwrite

Device Family Selection Guidelines

• Refer to the Product Selector tool on the Intel^® website to quickly find and compare the specifications and features of Intel^® FPGA devices and development kits.
• Once you identify the target device family, refer to the device family technical documentation for detailed device characteristics. Each device family includes complete documentation, including a datasheet and user guide or handbook. You can also view a summary of each device's resources by selecting a device in the Device dialog box (Assignments > Device)
  Figure 32. Device Dialog Box
• Consider whether the device family meets any requirements you have for high-speed transceivers, global or regional clock networks, and the number of phase-locked loops (PLLs)
• Consider the density requirements of your design. Devices with more logic resources and higher I/O counts can implement larger and more complex designs, but at a higher cost. Smaller devices use lower static power. Select a device larger than what your design requires if you may want to add more logic later in the design cycle, or to reserve logic and memory for on-chip debugging.
• Consider requirements for types of dedicated logic blocks, such as memory blocks of different sizes, or digital signal processing (DSP) blocks to implement certain arithmetic functions.

Selecting a migration device impacts pin placement because some pins may serve different functions in different device densities or package sizes. If you make pin assignments in the Intel^® Quartus^® Prime software, the Pin Migration View in the Pin Planner highlights pins that change function between your migration devices.

For IP cores that require additional license for production use, the Intel^® FPGA IP Evaluation Mode, allows you to program the FPGA to verify the IP in the hardware before you purchase the IP license. Refer to Introduction to Intel FPGA IP Cores for general information on using Intel^® FPGA IP cores.

You can use the Intel^® Quartus^® Prime Platform Designer system integration tool to use standard interfaces and speed-up system-level integration. Platform Designer components use Avalon^® standard interfaces for physical connections, allowing you to connect any logical device (either on-chip or off-chip) that has an Avalon interface. Platform Designer allows you to define system components in a GUI, and then automatically generates the required interconnect logic, along with clock-crossing and width adapters.

The Avalon standard includes two interface types:

• Avalon Memory-Mapped (Avalon-MM)—allow a component to use an address-mapped read or write protocol that connects master components to slave components.
• Avalon Streaming (Avalon-ST)—enables point-to-point connections between streaming components that send and receive data using a high-speed, unidirectional system interconnect between source and sink ports.

The technical documentation for each device family describes the available configuration options.

Power estimation and analysis helps you ensure that your design satisfies thermal and power supply requirements:

• Thermal—ensure that the cooling solution is sufficient to dissipate the heat generated by the device. The computed junction temperature must fall within normal device specifications.
• Power supply—ensure that the power supplies provide adequate current to support device operation.

Early Power Estimator (EPE) Spreadsheet

The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization for your design. Estimating power consumption early in the design cycle allows planning of power budgets and avoids unexpected results when designing the PCB.

You can manually enter data into the EPE spreadsheet, or use the Intel^® Quartus^® Prime software to generate device resource information for your design.

To manually enter data into the EPE spreadsheet, enter the device resources, operating frequency, toggle rates, and other parameters for your design. If you do not have an existing design, estimate the number of device resources used in your design, and then enter the data into the EPE spreadsheet manually.

If you have an existing design or a partially completed design, you can use the Intel^® Quartus^® Prime software to generate the Early Power Estimator File (.txt, .csv) to assist you in completing the EPE spreadsheet.

The EPE spreadsheet includes the Import Data macro that parses the information in the EPE File and transfers the information into the spreadsheet. If you do not want to use the macro, you can manually transfer the data into the EPE spreadsheet. For example, after importing the EPE File information into the EPE spreadsheet, you can add device resource information. If the existing Intel^® Quartus^® Prime project represents only a portion of your full design, manually enter the additional device resources you use in the final design.

Intel^® Quartus^® Prime Power Analyzer

After you complete your design, you can use the Intel^® Quartus^® Prime Power Analyzer to perform a complete post-fit power analysis to check the power consumption more accurately. The Power Analyzer provides an accurate estimation of power, ensuring that thermal and supply limitations are met.

Intel provides tools for SSN analysis and estimation, including SSN characterization reports, an Early SSN Estimator (ESE) spreadsheet tool, and the SSN Analyzer in the Intel^® Quartus^® Prime software. SSN often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system. You must address SSN with estimation early in your system design, to minimize later board design changes. When your design is complete, verify your board design by performing a complete SSN analysis of your FPGA in the Intel^® Quartus^® Prime software.

Different synthesis tools may give different results for each design. To determine the best tool for your application, you can experiment by synthesizing typical designs for your application and coding style. Perform placement and routing in the Intel^® Quartus^® Prime software to get accurate timing analysis and logic utilization results.

The synthesis tool you choose may allow you to create an Intel^® Quartus^® Prime project and pass constraints, such as the EDA tool setting, device selection, and timing requirements that you specified in your synthesis project. You can save time when setting up your Intel^® Quartus^® Prime project for placement and routing.

Tool vendors frequently add new features, fix tool issues, and enhance performance for Intel devices, you must use the most recent version of third-party synthesis tools.

Use the simulator version that your Intel^® Quartus^® Prime software version supports for best results. You must also use the model libraries provided with your Intel^® Quartus^® Prime software version. Libraries can change between versions, which might cause a mismatch with your simulation netlist.

The Intel^® Quartus^® Prime in-system debugging tools offer different advantages and trade-offs, depending on the characteristics of your design. Consider the following debugging requirements when planning your design to support debugging tools:

• JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.
• Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic.
• Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging.
• Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which require I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required. Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation.
• Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core.
• Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the tapped node names do not change during synthesis.

  Table 9.  Factors to Consider When Using Debugging Tools During Design Planning Stages

  Design Planning Factor	Signal Tap Logic Analyzer	System Console	In-System Memory Content Editor	Logic Analyzer Interface (LAI)	Signal Probe	In-System Sources and Probes	Virtual JTAG IP Core
  JTAG connections	Yes	Yes	Yes	Yes	—	Yes	Yes
  Additional logic resources	—	Yes	—	—	—	—	Yes
  Reserve device memory	Yes	Yes	—	—	—	—	—
  Reserve I/O pins	—	—	—	Yes	Yes	—	—
  Instantiate IP core in your HDL code	—	—	—	—	—	Yes	Yes

In a synchronous design, a clock signal triggers all events. When you meet all register timing requirements, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.

Clock signals have a large effect on the timing accuracy, performance, and reliability of your design. Problems with clock signals can cause functional and timing problems in your design. Use dedicated clock pins and clock routing for best results, and if you have PLLs in your target device, use the PLLs for clock inversion, multiplication, and division. For clock multiplexing and gating, use the dedicated clock control block or PLL clock switchover feature instead of combinational logic, if these features are available in your device. If you must use internally-generated clock signals, register the output of any combinational logic used as a clock signal to reduce glitches.

Consider the architecture of the device you choose so that you can use specific features in your design. For example, the control signals should use the dedicated control signals in the device architecture. Sometimes, you might need to limit the number of different control signals used in your design to achieve the best results.

If you design memory and DSP functions, you must understand the target architecture of your device so you can use the dedicated logic block sizes and configurations. Follow the coding guidelines for inferring Intel^® FPGA IP and targeting dedicated device hardware, such as memory and DSP blocks.

Designers commonly use a synchronization chain to minimize the occurrence of metastable events. Ensure that your design accounts for synchronization between any asynchronous clock domains. Consider using a synchronizer chain of more than two registers for high-frequency clocks and frequently-toggling data signals to reduce the chance of a metastability failure.

You can use the Intel^® Quartus^® Prime software to analyze the average mean time between failures (MTBF) due to metastability when a design synchronizes asynchronous signals, and optimize your design to improve the metastability MTBF. The MTBF due to metastability is an estimate of the average time between instances when metastability could cause a design failure. A high MTBF (such as hundreds or thousands of years between metastability failures) indicates a more robust design. Determine an acceptable target MTBF given the context of your entire system and the fact that MTBF calculations are statistical estimates.

The Intel^® Quartus^® Prime software can help you determine whether you have enough synchronization registers in your design to produce a high enough MTBF at your clock and data frequencies.

Although the source code may be hierarchical, the Compiler flattens and synthesizes all the design logic. Whenever you re-compile the project, the Compiler re-performs all available logic and placement optimizations on the entire design.

The flat compilation flow does not require any planning for design partitions. However, because the Intel^® Quartus^® Prime software recompiles the entire design whenever you change your design, flat design practices may require more overall compilation time for large designs. Additionally, you may find that the results for one part of the design change when you change a different part of your design. You can run Rapid Recompile to preserve portions of previous placement and routing in subsequent compilations. Rapid Recompile can reduce your compilation time in a flat or partitioned design when you make small changes to your design.

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
• Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel^® Quartus^® Prime IP file (.ip) for an IP variation in Intel^® Quartus^® Prime Pro Edition projects.

• Use the Presets window to apply preset parameter values for specific applications (for select cores).
• Use the Details window to view port and parameter descriptions, and click links to documentation.
• Click Generate > Generate Testbench System to generate a testbench system (for select cores).
• Click Generate > Generate Example Design to generate an example design (for select cores).
• Click Validate System Integrity to validate a system's generic components against companion files. (Platform Designer systems only)
• Click Sync All System Info to validate a system's generic components against companion files. (Platform Designer systems only)

The IP Catalog is also available in Platform Designer (View > IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Intel^® Quartus^® Prime IP Catalog. Refer to Creating a System with Platform Designer or Creating a System with Platform Designer for information on use of IP in Platform Designer and Platform Designer, respectively.

• Simulate the behavior of a licensed Intel^® FPGA IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.

Intel^® FPGA IP Evaluation Mode supports the following operation modes:

• Tethered—Allows running the design containing the licensed Intel^® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel^® Quartus^® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel^® Quartus^® Prime software, and requires no Intel^® Quartus^® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
• Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel^® Quartus^® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.

When the evaluation time expires for any licensed Intel^® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel^® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.

You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel^® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.

Intel^® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel^® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel^® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center.

The Intel^® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel^® Quartus^® Prime design software, and all unlicensed IP cores.

The following settings control how the Intel^® Quartus^® Prime software manages IP cores in a project:

• Do not manually edit or write your own .qsys, .ip, or .qip file. Use the Intel^® Quartus^® Prime software tools to create and edit these files.
  Note: When generating IP cores, do not generate files into a directory that has a space in the directory name or path. Spaces are not legal characters for IP core paths or names.
• When you generate an IP core using the IP Catalog, the Intel^® Quartus^® Prime software generates a .qsys (for Platform Designer-generated IP cores) or a .ip file (for Intel^® Quartus^® Prime Pro Edition) or a .qip file. The Intel^® Quartus^® Prime Pro Edition software automatically adds the generated .ip to your project. In the Intel^® Quartus^® Prime Standard Edition software, add the .qip to your project. Do not add the parameter editor generated file (.v or .vhd) to your design without the .qsys or .qip file. Otherwise, you cannot use the IP upgrade or IP parameter editor feature.
• Plan your directory structure ahead of time. Do not change the relative path between a .qsys file and it's generation output directory. If you must move the .qsys file, ensure that the generation output directory remains with the .qsys file.
• Do not add IP core files directly from the /quartus/libraries/megafunctions directory in your project. Otherwise, you must update the files for each subsequent software release. Instead, use the IP Catalog and then add the .qip to your project.
• Do not use IP files that the Intel^® Quartus^® Prime software generates for RAM or FIFO blocks targeting older device families (even though the Intel^® Quartus^® Prime software does not issue an error). The RAM blocks that Intel^® Quartus^® Prime generates for older device families are not optimized for the latest device families.
• When generating a ROM function, save the resulting .mif or .hex file in the same folder as the corresponding IP core's .qsys or .qip file. For example, moving all of your project's .mif or .hex files to the same directory causes relative path problems after archiving the design.
• Always use the Intel^® Quartus^® Prime ip-setup-simulation and ip-make-simscript utilities to generate simulation scripts for each IP core or Platform Designer system in your design. These utilities produce a single simulation script that does not require manual update for upgrades to Intel^® Quartus^® Prime software or IP versions, as Simulating Intel FPGA IP Cores describes.

• To upgrade a single IP core at the command-line, type the following command:

  quartus_sh –ip_upgrade –variation_files <my_ip>.<qsys,.v, .vhd> \
       <quartus_project>
  
  Example:
  quartus_sh -ip_upgrade -variation_files mega/pll25.qsys hps_testx

• To simultaneously upgrade multiple IP cores at the command-line, type the following command:

  quartus_sh –ip_upgrade –variation_files “<my_ip1>.<qsys,.v, .vhd>> \
       ;  <my_ip_filepath/my_ip2>.<hdl>”  <quartus_project>
  
  Example:
  quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.qsys;mega/pll3.qsys" hps_testx

Adding the following Verilog or VHDL pragma to your RTL, along with the public key, enables the Intel^® Quartus^® Prime software to use the key to decrypt IP core files.

Verilog/SystemVerilog Encryption Pragma (Third-Party Tools):

`pragma protect key_keyowner="Intel Corporation"
`pragma protect data_method="aes128-cbc"
`pragma protect key_method="rsa"
`pragma protect key_keyname="Intel-FPGA-Quartus-RSA-1"
`pragma protect key_public_key
<encrypted session key>

`pragma protect begin
`pragma protect end

VHDL Encryption Pragma (Third-Party Tools):

`protect key_keyowner = “Intel Corporation”
`protect data_method="aes128-cbc"
`protect key_method = “rsa”
`protect key_keyname = “Intel-FPGA-Quartus-RSA-1”
`protect key_block
<Encrypted session key>

Only file encryption with a third-party tool requires the public encryption key. File encryption with the Intel^® Quartus^® Prime Pro Edition software does not require the public encryption key.

Use one of the following methods to obtain the public encryption key:

• To obtain the encryption key, login or register for a My-Intel account, and then submit an Intel^® Premier Support case requesting the encryption key.
• If you are ineligible for Intel^® Premier Support, you can submit a question regarding the "IEEE 1735 Encryption Public Key" to the Intel^® Community Forum for assistance.

Intel^® Quartus^® Prime Pro Edition projects do not support compilation in other Quartus software products, and vice versa. The Intel^® Quartus^® Prime Pro Edition software generates an error if the Compiler detects other Quartus software product's features in project files.

Before migrating other Quartus software product projects, click Project > Archive Project to save a copy of your original project before making modifications for migration.

While the current version of the Intel^® Quartus^® Prime Pro Edition software still accepts entity names in the .qsf, the Compiler ignores the entity name. The Compiler generates a warning message upon detection of an entity names in the .qsf. Whenever possible, you should remove entity names from assignments, and discontinue reliance on entity-based assignments. Future versions of the Intel^® Quartus^® Prime Pro Edition software may eliminate all support for entity-based assignments.

Use .sdc files from other Quartus software products without modification. However, any scripts that include custom processing of names that the .sdc command returns, such as get_registers may require modification. Your scripts must reflect that returned strings do not include entity names.

The .sdc commands respect wildcard patterns containing entity names. Review the Timing Analyzer reports to verify application of all constraints. The following example illustrates differences between functioning and non-functioning .sdc scripts:

# Apply a constraint to all registers named "acc" in the entity "counter".
# This constraint functions in both SE and PE, because the SDC
# command always understands wildcard patterns with entity names in them
set_false_path –to [get_registers  “counter:*|*acc”]

# This does the same thing, but first it converts all register names to 
# strings, which includes entity names by default in the SE
# but excludes them by default in the PE. The regexp will therefore
# fail in PE by default.
#
# This script would also fail in the SE, and earlier
# versions of Quartus II, if entity name display had been disabled
# in the QSF.
set all_reg_strs [query_collection –list –all [get_registers *]]
foreach keeper $all_reg_strs {
   if {[regexp {counter:*|:*acc} $keeper]} {
      set_false_path –to $keeper
   }
}

# This script requires that entity names be included
# due to custom name processing
set old_mode [set_project_mode -get_mode_value always_show_entity_name]
set_project_mode -always_show_entity_name on

<... the rest of your script goes here ...>

# Restore the project mode
set_project_mode -always_show_entity_name $old_mode

Avoid dependence on synthesis-generated names due to frequent changes in name generation. In addition, verify the names of duplicated registers and PLL clock outputs to ensure compatibility with any script or constraint.

PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
    PHYSICAL_SYNTHESIS_COMBO_LOGIC
    PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
    PHYSICAL_SYNTHESIS_REGISTER_RETIMING
    PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
    PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA 

If your top-level entity is a Verilog HDL configuration, set the Verilog HDL configuration, rather than the module, as the top-level entity.

config mid_config;
design good_lib.mid;
instance mid.sub_inst use good_lib.sub;
endconfig

module test (input a1, output b);
mid_config mid_inst ( .a1(a1), .b(b)); 
// in other Quartus products preceding line would have been: 
//mid mid_inst ( .a1(a1), .b(b));
endmodule

module mid (input a1, output b);
sub sub_inst (.a1(a1), .b(b));
endmodule

Intel^® Quartus^® Prime Pro Edition synthesis allows use of unsized constants in .sv files for uses other than WYSIWYG instantiation. Ensure that your RTL code does not use unsized constants for WYSIWYG instantiation. For example, specify a sized literal, such as 2'b11, rather than '1.

• vhdl(verilog)_input_version Pragma—allows change to the input version in the middle of an input file. For example, to change VHDL 1993 to VHDL 2008. For Intel^® Quartus^® Prime Pro Edition migration, specify the input version for each file in the .qsf.
• library Pragma—allows changes to the VHDL library into which files compile. For Intel^® Quartus^® Prime Pro Edition migration, specify the compilation library in the .qsf.

To avoid syntax errors, remove all unconnected and non-existent ports for Intel^® Quartus^® Prime Pro Edition migration.

Refer to the following user guides for comprehensive information on all phases of the Intel^® Quartus^® Prime Pro Edition FPGA design flow.