Intel Quartus Prime Pro Edition User Guide: Getting Started
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.3 |
1. Introduction to Intel Quartus Prime Pro Edition
This user guide describes basic concepts and operation of the Intel® Quartus® Prime Pro Edition design software, including GUI and project structure basics, initial design planning, use of Intel FPGA IP, and migration to Intel® Quartus® Prime Pro Edition. This software provides a complete design environment for the most advanced Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX FPGA and SoC designs.
The Intel® Quartus® Prime software GUI supports easy design entry, fast design processing, straightforward device programming, and integration with other industry-standard EDA tools. The user interface makes it easy for you to focus on your design—not on the design tool. The modular Compiler streamlines the FPGA development process, and ensures the highest performance for the least effort.
The Intel® Quartus® Prime Pro Edition software expands on the capabilities of the Intel® Quartus® Prime Standard Edition, and provides unique features that support the latest Intel® FPGAs. Select the Intel® Quartus® Prime software edition that provides the device support and features you require, as Selecting an Intel Quartus Prime Software Edition describes.
The Intel® Quartus® Prime Pro Edition software offers flexible design methodologies, advanced synthesis, and supports the latest Intel® FPGA architectures and hierarchical design flows. The Compiler provides powerful and customizable design processing to achieve the best possible design implementation in silicon. The following features are unique to the Intel® Quartus® Prime Pro Edition:
- Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation to reach the highest performance in Intel® Agilex™ and Intel® Stratix® 10 devices.
- Intel® Quartus® Prime Pro Edition synthesis—integrates new, stricter language parser supporting all major IEEE RTL languages, with enhanced algorithms, and parallel synthesis capabilities. Added support for SystemVerilog 2009.
- Hierarchical project structure—preserve individual post-synthesis, post-placement, and post-place and route results for each design instance. Allows optimization without impacting other partition placement or routing.
- Incremental Fitter Optimizations—run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports.
- Faster, more accurate I/O placement—plan interface I/O in Interface Planner.
- Platform Designer—builds on the system design and custom IP integration capabilities of Platform Designer. Platform Designer in Intel® Quartus® Prime Pro Edition introduces hierarchical isolation between system interconnect and IP components.
- Partial Reconfiguration—reconfigure a portion of the FPGA, while the remaining FPGA continues to function.
- Block-Based Design Flows—preserve and reuse design blocks at various stages of compilation.
1.1. Selecting an Intel Quartus Prime Software Edition
- Select the
Intel®
Quartus® Prime Pro Edition if you are
beginning a new
Intel®
Arria® 10,
Intel®
Cyclone® 10 GX,
Intel®
Stratix® 10 or
Intel®
Agilex™
design, or to take
advantage of the unique features of
Intel®
Quartus® Prime Pro Edition.Figure 2. Intel Quartus Prime Feature Support Matrix
- Select the Intel® Quartus® Prime Standard Edition software if your design must target Arria® V, Arria® , Intel® Cyclone® 10 LP, Cyclone IV, Cyclone V, or MAX® series devices, and you do not want to migrate you design to a device that Intel® Quartus® Prime Pro Edition supports.
-
Intel®
Quartus® Prime Pro Edition software does not support
the following
Intel®
Quartus® Prime Standard Edition
features:
- I/O Timing Analysis
- NativeLink third party tool integration (other third-party tool integration available)
- Video and Image Processing Suite IP Cores
- Talkback features
- Various register merging and duplication settings
- Saving a node-level netlist as .vqm
Intel replaces the following Altera tool names in the Intel® Quartus® Prime software:
Altera Name | Intel® Name |
---|---|
Qsys | Platform Designer |
BluePrint | Interface Planner |
TimeQuest | Timing Analyzer |
EyeQ | Eye Viewer |
JNEye | Advanced Link Analyzer |
1.2. Introduction to Intel Quartus Prime Pro Edition Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.09.28 | 20.3 |
|
2019.09.30 | 19.3 |
|
2018.09.24 | 18.1 |
|
2018.05.07 | 18.0 | Initial release as separate chapter of Getting Started User Guide. Separated Migrating to Intel® Quartus® Prime Pro Edition as independent chapter in user guide. |
2017.11.06 | 17.1 |
|
2017.05.08 | 17.0 |
|
2016.10.31 | 16.1 |
|
2016.05.03 | 16.0 |
|
2015.11.02 | 15.1 |
|
2. Managing Intel Quartus Prime Projects
Click File > New Project Wizard to quickly setup and open a new project.
After you create or open a project, the GUI displays integrated information and controls for the open project.
2.1. Viewing Basic Project Information
Project Tasks Pane
The Tasks pane (View > Tasks) provides one-click launch of common project tasks, such as creating design files, specifying project settings, running compilation, debug and timing closure, and device programming.
The Project Navigator
The Project Navigator (View > Project Navigator) displays information about the elements of your project, such as the design files, IP components, and your project hierarchy (after elaboration). You can right-click items in the Project Navigator to locate or perform actions on the elements of your project. The Project Navigator organizes information on the Files, Hierarchy, Design Units, and IP Components tabs.Project Navigator Tab | Description |
---|---|
Files | Lists all design files in the current project.
Right-click design files in this tab to run these commands:
|
Hierarchy | Provides a visual representation of the project hierarchy, specific resource usage information, and device and device family information. Right-click items in the hierarchy to Locate, Set as Top-Level Entity, or define Logic Lock regions or design partitions. |
Design Units | Displays the design units in the project. Right-click a design unit to Locate in Design File. |
IP Components | Displays the design files that make up the IP instantiated in the project, including Intel® FPGA IP, Platform Designer components, and third-party IP. Click Launch IP Upgrade Tool from this tab to upgrade outdated IP components. Right-click any IP component to Edit in Parameter Editor. |
2.1.1. Using the Compilation Dashboard
The Compilation Dashboard appears by default when you open a project, or you can click Compilation Dashboard in the Tasks window to re-open it.
- Click the Pencil icon to edit settings for that stage of the compilation flow.
- Click any Compiler stage to run one or more Compiler stage.
- Click the Report, RTL Viewer, Technology Map Viewer, Timing Analyzer, or Snapshot Viewer icons for analysis of stage results.
As the Compiler progresses through the flow, the dashboard updates the status of each module, and enables icons that you can click for reports and analysis.
2.1.2. Viewing Project Reports
Review the detailed information in these the compilation reports to determine correct implementation. Right-click report data to locate and edit the source in project files.
2.1.3. Viewing Project Messages
- Processing tab—displays messages from the most recent process
- System tab—displays messages unrelated to design processing
- Search—locates specific messages
2.1.3.1. Suppressing Message Display
- Suppress Message—suppresses all messages that match the exact text you specify.
- Suppress Messages with Matching ID—suppresses all messages that match the message ID number you specify, ignoring variables.
- Suppress Messages with Matching Keyword—suppresses all messages that match the keyword or hierarchy you specify.
- Message Suppression Manager—allows you to create and edit message suppression rules. You can define message suppression rules by message text, message ID number, or keyword.
Suppressing Messages by Design Entity
You can optionally suppress messages by design entity without modifying HDL. Entity-based message suppression can be helpful to eliminate insignificant warnings for specific IP components or design entities that may be obscuring other more important warnings.
To suppress messages by design entity, add the following line to the project .qsf, or to the .qip file for stand-alone IP components:
set_global_assignment -name MESSAGE_DISABLE -entity <name>
- You cannot suppress error or Intel legal agreement messages.
- Suppressing a message also suppresses any submessages.
- A root message does not display if you suppress all of the root message's submessages.
- Message suppression is project revision-specific. Derivative project revisions inherit any suppression.
- You cannot edit messages or suppression rules during compilation.
- Messages are written to stdout when you use command-line executables.
2.1.4. Automated Problem Reports
To disable or enable automatic sending of problem reports, follow these steps:
- Click Tools > Options.
- Click the Internet Connectivity tab.
- Under Problem report, turn on or
off Always send report to Intel when internal error
occurs (command-line only).Figure 10. Problem Report Option
2.2. Intel Quartus Prime Project Contents
File Type | Contains | To Edit | Format |
---|---|---|---|
Project file | Project and revision name | File > New Project Wizard | Intel® Quartus® Prime Project File (.qpf) |
Settings file | Lists design files, entity settings, target device, synthesis directives, placement constraints | Assignments > Settings | Intel® Quartus® Prime Settings File (.qsf) |
Quartus database | Project compilation results | Project > Export Design | Quartus Database File (.qdb) |
Partition database | Partition compilation results | Project > Export Design Partition | Partition Database File (.qdb) |
Timing constraints | Clock properties, exceptions, setup/hold | Tools > Timing Analyzer | Synopsys Design Constraints File (.sdc) |
Logic design files | RTL and other design source files | File > New | All supported HDL files |
Programming files | Device programming image and information | Tools > Programmer |
SRAM Object File (.sof) Programmer Object File (.pof) |
IP core files | IP core variation parameterization | Tools > IP Catalog | Intel® Quartus® Prime IP File (.ip) |
Platform Designer system files | System definition | Tools > Platform Designer | Platform Designer System File (.qsys) |
EDA tool files | Scripts for third-party EDA tools | Assignments > Settings > EDA Tool Settings | Verilog
Output File (.vo) VHDL Output File (.vho) Verilog Quartus Mapping File (.vqm) |
Archive files | Complete project as single compressed file | Project > Archive Project | Intel® Quartus® Prime Archive File (.qar) |
2.2.1. Project File Best Practices
-
Avoid manually editing Intel® Quartus® Prime data files, such as the Intel® Quartus® Prime Project File (.qpf), Intel® Quartus® Prime Settings File (.qsf), Quartus IP File (.ip), or Platform Designer System File (.qsys). Syntax errors in these files cause errors during compilation. For example, the software may ignore improperly formatted settings and assignments.
-
Do not compile multiple projects into the same directory. Instead, use a separate directory for each project.
-
By default, the Intel® Quartus® Prime software saves all project output files, such as Text-Format Report Files (.rpt), in the project directory. If you want to change the location of output files, instead of manually moving project output files, click Assignments > Settings > Compilation Process Settings, and specify the Save project output files in specified directory option.
2.3. Managing Project Settings
Global Project Settings
To access global project settings, click Assignments > Settings, or click Settings on the Tasks pane.
The Settings dialog box provides access to settings that control project design files, synthesis, Fitter, and timing constraints, operating conditions, EDA tool file generation, programming file generation, and other project-level settings.
Additionally, the Assignment Editor (Assignments > Assignment Editor) provides a spreadsheet-like interface for specifying instance-specific settings and constraints.
2.3.1. Specifying the Target Device or Board
- Open a project in the Intel® Quartus® Prime software.
-
Click Assignments > Device.
Figure 13. Device Dialog Box
-
Specify either a target
Intel®
FPGA board or device for your project. When you
specify a board, the
Intel®
Quartus® Prime software
generates the appropriate pin assignments script for that board
automatically.
- To specify an
Intel®
FPGA
board or development kit for your project:
- Click the Board tab.
- Select the target device Family and a supported Development Kit. Click Yes if prompted to remove existing Location and I/O Standard pin assignments. The Intel® Quartus® Prime software creates the kit's baseline design and stores the design in <current_project_dir>/devkits/<design_name>. To retain all your existing pin assignments, click No.
- Select the desired development kit and click OK.
- To specify a device family for your project:
- On the Device tab, select the Family and Device name. The list of Available devices reflects your selections.
- To further refine your selection, specify options for the Package, Pin count, Core speed grade, Name filter, and Show advanced devices filters.
- From the Available devices, select your target device Name and click OK.
- To specify an
Intel®
FPGA
board or development kit for your project:
2.3.2. Optimizing Project Settings
The Intel® Quartus® Prime software includes several advisors to help you optimize your design and reduce compilation time. The advisors listed in the Tools > Advisors menu can provide recommendations based on your project settings and design constraints.
2.3.2.1. Optimize Settings with Design Space Explorer II
DSE II attempts multiple seeds to identify one meeting your requirements. DSE II can run different compilations on multiple computers in parallel to streamline timing closure.
2.3.2.2. Optimize Settings with Project Revisions
Use revisions to experiment with different settings while preserving the original. Optimize different revisions for separate applications:
- Create a unique revision to optimize a design for different criteria, such as by area in one revision and by fMAX in another revision.
- When you create a new revision the default Intel® Quartus® Prime settings initially apply.
- Create a revision of a revision to experiment with settings and constraints. The child revision includes all the assignments and settings of the parent revision.
You create, delete, and edit revisions in the Revisions dialog box. Each time you create a new project revision, the Intel® Quartus® Prime software creates a new .qsf using the revision name.
To compare each revision’s synthesis, fitting, and timing analysis results side-by-side, click Project > Revisions and then click Compare. In addition to viewing the compilation Results of each revision, you can also compare the Assignments for each revision. This comparison reveals how different optimization options affect your design.
2.3.2.3. Back-Annotate Optimized Assignments
Locking down placement of large blocks related to Clocks, RAMs, and DSPs can produce higher fMAX with less noise. Large blocks like RAMs and DSPs have heavier connectivity than regular LABs, complicating movement during placement. When a seed produces good results from suitable RAM and DSP placement, you can capture that placement with back-annotation. Subsequent compiles can then benefit from the high quality RAM and DSP placement from the good seed.
To back-annotate (copy) the device resource assignments from the last compilation to the project .qsf (or to a Tcl file) for use in the next compilation:
- Run a full compilation, or run the Fitter through at least the Place stage.
- Click Assignments > Back-Annotate Assignments.
- Under Assignments to back-annotate, specify whether you want to preserve Pin assignments, RAM assignments, DSP assignments, Clock assignments, and Clock Spine assignments in the back-annotation.
- In Filter, specify a text string (including wildcards) if you want to filter back-annotated assignments by entity name.
- Under Output, specify whether to save the back-annotated assignments to the .qsf or to a Tcl file. A default Tcl file name displays.
Alternatively, you can run back-annotation with the following quartus_cdb executable. The Shell command field displays the shell command constructed by the options that you specifying the GUI.
quartus_cdb chiptrip_nf --back_annotate --pin --ram --dsp --clocks \ --spines --file "<file>.tcl"
2.4. Managing Logic Design Files
The Intel® Quartus® Prime software includes full-featured schematic and text editors, as well as HDL templates to accelerate your design work. The Intel® Quartus® Prime software supports VHDL Design Files (.vhd), Verilog HDL Design Files (.v), SystemVerilog (.sv) and schematic Block Design Files (.bdf). In addition, you can combine your logic design files with Intel and third-party IP core design files, including combining components into a Platform Designer system (.qsys).
The New Project Wizard prompts you to identify logic design files. Add or remove project files by clicking Project > Add/Remove Files in Project. View the project’s logic design files in the Project Navigator.
Right-click files in the Project Navigator to:
- Open and edit the file
- Remove File from Project
- Set as Top-Level Entity for the project revision
- Create a Symbol File for Current File for display in schematic editors
- Edit file Properties
2.4.1. Including Design Libraries
The quartus2.ini file stores global library information.
- Click Assignment > Settings.
- Click Libraries and specify the Project Library name or Global Library name. Alternatively, you can specify project libraries with SEARCH_PATH in the .qsf, and global libraries in the quartus2.ini file.
2.4.2. Creating a Project Copy
The project copy includes separate copies of all design files, any .qsf files, and project revisions. You can use this technique to optimize project copies for different applications that require design file differences. For example, you can optimize one project to interface with a 32-bit data bus, and optimize a project copy to interface with a 64-bit data bus.
2.5. Managing Timing Constraints
Specify timing constraints in the Timing Analyzer (Tools > Timing Analyzer), or in an .sdc file. Specify constraints for clock characteristics, timing exceptions, and external signal setup and hold times before running analysis. The Timing Analyzer reports detailed information about the performance of your design compared with constraints in the Compilation Report panel.
Save the constraints you specify in the GUI in an industry-standard Synopsys Design Constraints File (.sdc). You can subsequently edit the text-based .sdc file directly. If you refer to multiple .sdc files in a parent .sdc file, the Timing Analyzer reads the .sdc files in the order you list.
2.6. Integrating Other EDA Tools
The Intel® Quartus® Prime software manages EDA tool files and provides the following integration capabilities:
- Compile all RTL and gate-level simulation model libraries for your device, simulator, and design language automatically (Tools > Launch Simulation Library Compiler).
- Include files generated by other EDA design entry or synthesis tools in your project as synthesized design files (Project > Add/Remove File from Project) .
- Automatically generate optional files for board-level verification (Assignments > Settings > EDA Tool Settings).
2.7. Exporting Compilation Results
You can export the .qdb for your entire project or for a design partition that you define in your project. When migrating the database for an entire project, you can export the compilation database in a version-compatible format to ensure compatibility for import to a later software version. Although you cannot directly read the contents of the .qdb file after export, you can view attributes of the database file in the Quartus Database File Viewer.
To Export Compilation Results For | Method | Description |
---|---|---|
Complete Design | Click Project > Export Design | Saves compilation results for the entire project in a version-compatible Quartus database file (.qdb) that you can import to another project or migrate to a later version of the Intel® Quartus® Prime software. You can export the results for the synthesized or final compilation snapshot. |
Design Partition | Click Project > Export Design Partition | Saves compilation results for a design partition as a Partition Database File (.qdb) that you can import to another project using the same version of the Intel® Quartus® Prime software. You can export the results for the synthesized or final compilation snapshot. |
2.7.1. Exporting a Version-Compatible Compilation Database
- In the Intel® Quartus® Prime software, open the project that you want to export.
-
Generate synthesis or final compilation results by running
one of the following commands:
- Click Processing > Start > Start Analysis & Synthesis to generate synthesized compilation results.
- Click Processing > Start Compilation to generate final compilation results.
-
Click Project > Export Design. Select the synthesized
or final
Snapshot.
Figure 19. Export Design Dialog Box
- Specify a name for the Quartus Database File to contain the exported results, and click OK.
- To include the exported design's settings and constraint files, copy the .qsf and .sdc files to the import project directory.
2.7.2. Importing a Version-Compatible Compilation Database
- Export a version-compatible compilation database for a complete design, as Exporting a Version-Compatible Compilation Database describes.
- In a newer version of the Intel® Quartus® Prime software, open the original project. Click Yes if prompted to open a project created with a different software version.
-
Click Project > Import Design and specify the Quartus Database
File. To remove previous results, turn on Overwrite existing project's databases
Figure 20. Import Design Dialog Box
- Click OK.
- When you compile the imported design, run only Compiler stages that occur after the stage the .qdb preserves, rather than running a full compilation. For example, if you import a version-compatible database that contains the synthesis snapshot, start compilation with the Fitter (Processing > Start > Start Fitter). If you import a version-compatible database the contains the final snapshot, start compilation with Timing Analysis (Signoff) (Processing > Start > Start Timing Analysis (Signoff)).
2.7.3. Creating a Design Partition
- In the Intel® Quartus® Prime software, open the project that you want to partition.
-
Generate synthesis or final compilation results by running one
of the following commands:
- Click Processing > Start > Start Analysis & Synthesis to generate synthesized compilation results.
- Click Processing > Start Compilation to generate final compilation results.
-
In the Project Navigator, right-click an instance in the
Hierarchy tab, click Design Partition > Set as Design Partition.
Figure 22. Creating a Design Partition from the Project Hierarchy
-
To view and edit all design partitions in the project, click
Assignments > Design Partitions Window.
Figure 23. Design Partitions Window
-
Specify the properties of the design partition in the Design
Partitions Window. The following settings are available:
Table 5. Design Partition Settings Option Description Partition Name Specifies the partition name. Each partition name must be unique and consist of only alphanumeric characters. The Intel® Quartus® Prime software automatically creates a top-level (|) "root_partition" for each project revision. Hierarchy Path Specifies the hierarchy path of the entity instance that you assign to the partition. You specify this value in the Create New Partition dialog box. The root partition hierarchy path is |. Type Double-click to specify one of the following partition types that control how the Compiler processes and implements the partition: - Default—Identifies a standard partition. The Compiler processes the partition using the associated design source files.
- Reconfigurable—Identifies a reconfigurable partition in a partial reconfiguration flow. Specify the Reconfigurable type to preserve synthesis results, while allowing refit of the partition in the PR flow.
- Reserved Core—Identifies a partition in a block-based design flow that is reserved for core development by a Consumer reusing the device periphery.
Preservation Level Specifies one of the following preservation levels for the partition: - Not Set—specifies no preservation level. The partition compiles from source files.
- synthesized—the partition compiles using the synthesized snapshot.
- final—the partition compiles using the final snapshot.
With Preservation Level of synthesized or final, changes to the source code do not appear in the synthesis.
Empty Specifies an empty partition that the Compiler skips. This setting is incompatible with the Reserved Core and Partition Database File settings for the same partition. The Preservation Level must be Not Set. An empty partition cannot have any child partitions. Partition Database File Specifies a Partition Database File (.qdb) that the Compiler uses during compilation of the partition. You export the .qdb for the stage of compilation that you want to reuse (synthesized or final). Assign the .qdb to a partition to reuse those results in another context. Entity Re-binding - PR Flow—specifies the entity that replaces the default persona in each implementation revision.
- Root Partition Reuse Flow —specifies the entity that replaces the reserved core logic in the consumer project.
Color Specifies the color-coding of the partition in the Chip Planner and Design Partition Planner displays. Post Synthesis Export File Automatically exports post-synthesis compilation results for the partition to the .qdb that you specify, each time Analysis & Synthesis runs. You can automatically export any design partition that does not have a preserved parent partition, including the root_partition. Post Final Export File Automatically exports post-final compilation results for the partition to the .qdb that you specify, each time the final stage of the Fitter runs. You can automatically export any design partition that does not have a preserved parent partition, including the root_partition.
2.7.4. Exporting a Design Partition
When you compile a design containing design partitions, the Compiler can preserve a synthesis or final snapshot of results for each partition. You can export the synthesized or final compilation results for individual design partitions with the Export Design Partition dialog box.
If the partition includes any entity-bound .sdc files, you can include those constraints in the .qdb. In addition, you can automate export of one or more partitions in the Design Partitions Window.
Manual Design Partition Export
Follow these steps to manually export a design partition with the Export Design Partition dialog box:
- Open a project and create one or more design partitions. Creating a Design Partition describes this process.
- Run synthesis (Processing > Start > Start Analysis & Synthesis) or full compilation (Processing > Start Compilation), depending on which compilation results that you want to export.
- Click Project > Export Design Partition, and specify one or more options in the Export Design Partition dialog box:
Figure 24. Export Design Partition Dialog Box
- Select the Partition name and the compilation Snapshot for export.
- To include any entity-bound .sdc files in the exported .qdb, turn on Include entity-bound SDC files for the selected partition.
- Click OK. The compilation results for the design partition exports to the file that you specify.
Automated Design Partition Export
Follow these steps to automatically export one or more design partitions following each compilation:
- Open a project containing one or more design partitions. Creating a Design Partition describes this process.
- To open the Design Partitions Window, click Assignments > Design Partitions Window.
- To automatically export a partition with synthesis results after each time you run synthesis, specify the a .qdb export path and file name for the Post Synthesis Export File option for that partition. If you specify only a file name without path, the file exports to the output_files directory after compilation.
- To automatically export a partition with final snapshot results each time you run the Fitter, specify a .qdb file name for the Post Final Export File option for that partition. If you specify only a file name without path, the file exports to the output_files directory after compilation.
.qsf Equivalent Assignment:
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_<FINAL|SYNTHESIZED> \ <hpath> -to <file_name>.qdb
2.7.5. Reusing a Design Partition
To reuse an exported design partition in another project, you assign the exported partition .qdb to an appropriately configured design partition in the target project via the Design Partition Window:
- Export a design partition with the appropriate snapshot, as Exporting a Design Partition describes.
- Open the target Intel® Quartus® Prime project that you want to reuse the exported partition.
- Click Processing > Start > Start Analysis & Elaboration.
- Click Assignments > Design Partitions Window, and then create an appropriately sized design partition to contain the logic and compilation results of the exported .qdb.
-
Click the Partition Database File
option for the new partition and select the exported .qdb file.
Figure 26. Partition Database File Setting in Design Partitions Window
- Specify any other properties of the design partition in the Design Partitions Window. The Compiler uses the partition's assigned .qdb as the source.
2.7.6. Viewing Quartus Database File Information
The Intel® Quartus® Prime software automatically stores metadata about the project of origin when you export a Quartus Database File (.qdb). The Intel® Quartus® Prime software automatically stores metadata about the project of origin and resource utilization when you export a Partition Database File (.qdb) from your project. You can then use the Quartus Database File Viewer to display the attributes any of these .qdb files.
- In the Intel® Quartus® Prime software, click File > Open, select Design Files for Files of Type, and select a .qdb file.
-
Click Open. The Quartus
Database File Viewer displays project and resource utilization attributes of the .qdb.
Alternatively, run the following command-line equivalent:
quartus_cdb --extract_metadata --file <archive_name.qdb> \ --type quartus --dir <extraction_directory> \ [--overwrite]
2.7.6.1. QDB File Attribute Types
The Quartus Database Viewer can display the following attributes of a .qdb file:
QDB Attribute Types | Attribute | Example |
Project Information |
Contents | Partition |
Date | Thu Jan 23 10:56:23 2018 | |
Device | 10AX016C3U19E2LG | |
Entity (if Partition) | Counter | |
Family | Arria 10 | |
Partition Name | root_partition | |
Revision Name | Top | |
Revision Type | PR_BASE | |
Snapshot | synthesized | |
Version | 18.1.0 Pro Edition | |
Version-Compatible | Yes | |
Resource Utilization (exported for partition QDB only) |
For synthesized snapshot partition lists data from the Synthesis Resource Usage Summary report. |
Average fan-out.16 Dedicated logic registers:14 Estimate of Logic utilization:1 I/O pins:35 Maximum fan-out:2 Maximum fan-out node:counter[23] Total DSP Blocks:0 Total fan-out:6 ... |
For the final snapshot partition, lists data from the Fitter Partition Statistics report. |
Average fan-out:.16 Combinational ALUTs: 16 I/O Registers M20Ks ... |
2.7.7. Clearing Compilation Results
- Click Project > Clean Project.
- Select All revisions to clear the databases for all revisions of the current project, or specify a Revision name to clear only the revision’s database you specify.
- Click OK. A message indicates when the database is clean.
2.8. Migrating Projects Across Operating Systems
2.8.1. Migrating Design Files and Libraries
- Use appropriate case for your platform in file path references.
- Use a character set common to both platforms.
- Do not change the forward‑slash (/) and back‑slash (\) path separators in the .qsf. The Intel® Quartus® Prime software automatically changes all back‑slash (\) path separators to forward‑slashes (/ )in the .qsf.
- Observe the target platform’s file name length limit.
- Use underscore instead of spaces in file and directory names.
- Change library absolute path references to relative paths in the .qsf.
- Ensure that any external project library exists in the new platform’s file system.
- Specify file and directory paths as relative to the project directory. For example, for a project titled foo_design, specify the source files as: top.v, foo_folder /foo1.v, foo_folder /foo2.v, and foo_folder/bar_folder/bar1.vhdl.
- Ensure that all the subdirectories are in the same hierarchical structure and relative path as in the original platform.

2.8.1.1. Use Relative Paths
For example, in the directory structure shown you can specify top.v as ../source/top.v and foo1.v as ../source/foo_folder/foo1.v.

2.8.2. Design Library Migration Guidelines
- The project directory takes precedence over the project libraries.
- For Linux, the Intel® Quartus® Prime software creates the file in the altera.quartus directory under the <home> directory.
- All library files are relative to the libraries. For example, if you specify the user_lib1 directory as a project library and you want to add the /user_lib1/foo1.v file to the library, you can specify the foo1.v file in the .qsf as foo1.v. The Intel® Quartus® Prime software includes files in specified libraries.
- If the directory is outside of the project directory, an absolute path is created by default. Change the absolute path to a relative path before migration.
- When copying projects that
include libraries, you must either copy your project library files along with
the project directory or ensure that your project library files exist in the
target platform.
- On Windows*, the Intel® Quartus® Prime software searches for the quartus2.ini file in the following directories and order:
- USERPROFILE, for example, C:\Documents and Settings\<user name>
- Directory specified by the TMP environmental variable
- Directory specified by the TEMP environmental variable
- Root directory, for example, C:\
2.9. Archiving Projects
Use this technique to share projects between designers, or to transfer your project to a new version of the Intel® Quartus® Prime software, or to Intel support. Optionally add compilation results, Platform Designer system files, and third-party EDA tool files to the archive.
2.9.1. Manually Adding Files To Archives
- Click Project > Archive Project and specify the archive file name.
- Click Advanced.
- Select the File set for archive or select Custom. Turn on File subsets for the archive.
- Click Add and select Platform Designer system or EDA tool files. Click OK.
- Click Archive.
2.9.2. Archiving Projects for Service Requests
To identify and include appropriate archive files for an Intel service request:
- Click Project > Archive Project and specify the archive file name.
- Click Advanced.
- In File
set, select Service
request to include files for Intel Support.
- Project source and setting files (.v, .vhd, .vqm, .qsf, .sdc, .qip, .qpf, .cmp)
- Automatically detected source files (various)
- Programming output files (.jdi, .sof, .pof)
- Report files (.rpt, .pin, .summary, .smsg)
- Click OK, and then click Archive.
2.9.3. Using External Revision Control
While Intel® Quartus® Prime project revisions preserve various project setting and constraint combinations, external revision control systems can also track and merge RTL source code, simulation testbenches, and build scripts. External revision control supports design file version experimentation through branching and merging different versions of source code from multiple designers. Refer to your external revision control documentation for setup information.
2.9.3.1. Files to Include In External Revision Control
- Logic design files (.v, .vdh, .bdf, .edf, .vqm)
- Timing constraint files (.sdc)
- Quartus project settings and constraints (.qdf, .qpf, .qsf)
- IP files (.ip, .v, .sv, .vhd, .qip, .sip, .qsys)
- Platform Designer-generated files (.qsys, .ip, .sip)
- EDA tool files (.vo, .vho )
Generate or modify these files manually if you use a scripted design flow. If you use an external source code control system, check-in project files anytime you modify assignments and settings.
2.10. Command-Line Interface
- Create a text file with the extension .tcl that contains your assignments in Tcl format.
- Source the Tcl script file by adding the following line to the .qsf: set_global_assignment -name SOURCE_TCL_SCR IPT_FILE <file name> .
2.10.1. Project Revision Commands
create_revision Command
create_revision defines the properties of a new project revision.
create_revision <name> -based_on <revision_name> -set_current -new_rev_type \ <rev_type> -root_partition_qdb_file <root qdb>
Option | Description |
---|---|
based_on (optional) | Specifies the revision name on which the new revision bases its settings. |
set_current (optional) | Sets the new revision as the current revision. |
-new_rev_type | Specifies a base or impl (implementation) type for a new revision. |
root_partition_qdb_file | Specifies the name of a static region .qdb if already known when creating a revision. |
get_project_revisions Command
get_project_revisions returns a list of all revisions in the project.
get_project_revisions <project_name>
delete_revision Command
delete_revision deletes the revision you specify from your project.
delete_revision <revision name>
set_current_revision Command
set_current_revision sets the revision you specify as the current revision.
set_current_revision -force <revision name>
2.10.2. Project Archive Commands
project_archive Command
project_archive archives your project into a single, compressed .qar file.
project_archive <name>.qar
Options | Description |
---|---|
-all_revisions | Includes all revisions of the current project in the archive. |
-common_directory /<name> | Preserves original project directory structure in specified subdirectory. |
-include_libraries | Includes libraries in archive. |
-include_outputs | Includes output files in archive. |
-use_file_set <file_set> | Includes specified fileset in archive. |
-version_compatible_database | Includes version-compatible database files in archive. |
restore_archive Command
Restores an archived project to a destination directory with optional overwriting of current contents.
project_restore <name>.qar -destination <directory name> -overwrite
2.10.3. Project Database Commands
export_database Command
export_design exports the specified project database to the .qdb file you specify.
These commands require the quartus_cdb executable.
quartus_cdb <revision name> --export_design --file <file name>.qdb \ --snapshot <synthesized/final>
import_database Command
import_design imports the specified project database to the .qdb file you specify.
quartus_cdb <revision name> --import_design --file <file name>.qdb
export_block Command
export_block exports the specified partition database to the .qdb file you specify.
quartus_cdb -r <project name> -c <revision name> --export_block \ <partition name> --snapshot <name> --file <file name>.qdb
2.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
The command-line arguments to the quartus_cdb executable in the Quartus Prime Pro software are export_design and import_design. The exported version-compatible design files are archived in a file (with a .qdb extension). This differs from the Intel® Quartus® Prime Standard Edition software, which writes all files to a directory.
In the Intel® Quartus® Prime Standard Edition software, the flow exports both post-map and post-fit databases. In the Intel® Quartus® Prime Pro Edition software, the export command requires the snapshot argument to indicate the target snapshot to export. If the specified snapshot has not been compiled, the flow exits with an error. In ACDS 16.0, export is limited to “synthesized” and “final” snapshots.
quartus_cdb <project_name> [-c <revision_name>] --export_design --snapshot <snapshot_name> --file <filename>.qdb
The import command takes the exported *.qdb file and the project to which you want to import the design.
quartus_cdb <project_name> [-c <revision_name>] --import_design --file <archive>.qdb [--overwrite] [--timing_analysis_mode]
The --timing_analysis_mode option is only available for Intel® Arria® 10 designs. The option disables legality checks for certain configuration rules that may have changed from prior versions of the Intel® Quartus® Prime software. Use this option only if you cannot successfully import your design without it. After you have imported a design in timing analysis mode, you cannot use it to generate programming files.
2.11. Managing Projects Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.09.28 | 20.3 |
|
2020.05.01 | 20.1 |
|
2019.09.30 | 19.3 |
|
2018.09.24 | 18.1 |
|
2018.05.07 | 18.0.0 |
|
Date | Version | Changes |
---|---|---|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.03 | 16.0.0 |
|
2016.02.09 | 15.1.1 |
|
2015.11.02 | 15.1.0 |
|
2015.05.04 | 15.0.0 |
|
2014.12.15 | 14.1.0 |
|
2014.08.18 |
14.0a10.0 |
|
2014.06.30 | 14.0.0 |
|
November 2013 | 13.1.0 |
|
May 2013 | 13.0.0 |
|
June 2012 | 12.0.0 |
|
November 2011 | 10.1.1 | Template update. |
December 2010 | 10.1.0 |
|
3. Design Planning
3.1. Design Planning
By default, the Intel® Quartus® Prime software optimizes designs for the best overall results; however, you can adjust settings to better optimize one aspect of your design, such as performance, routability, area, or power utilization. Consider your own design priorities and trade-offs when reviewing the techniques in this chapter. For example, certain device features, density, and performance requirements can increase system cost. Signal integrity and board issues can impact I/O pin locations. Power, timing performance, and area utilization all affect one another. Compilation time is affected when optimizing these priorities.
Determining your design priorities early on helps you to choose the best device, tools, features, and methodologies for your design.
3.2. Create a Design Specification and Test Plan
In addition, creating a test plan helps you to design for verification and ease of manufacture. For example, your test plan can include validation of interfaces incorporated in your design. To perform any built-in self-test functions to drive interfaces, you can use a UART interface with a Nios® II processor inside the FPGA device.
If more than one designer contributes to the design, consider a common design directory structure or source control system to make design integration easier. Consider whether you want to standardize on an interface protocol for each design block.
3.3. Plan for the Target Device
Device Family Selection Guidelines
- Refer to the Product Selector tool on the Intel® website to quickly find and compare the specifications and features of Intel® FPGA devices and development kits.
- Once you identify the target device family, refer to the device family
technical documentation for detailed device characteristics. Each device family
includes complete documentation, including a datasheet and user guide or
handbook. You can also view a summary of each device's resources by selecting a
device in the Device dialog box
(Assignments > Device)
Figure 32. Device Dialog Box
- Consider whether the device family meets any requirements you have for high-speed transceivers, global or regional clock networks, and the number of phase-locked loops (PLLs)
- Consider the density requirements of your design. Devices with more logic resources and higher I/O counts can implement larger and more complex designs, but at a higher cost. Smaller devices use lower static power. Select a device larger than what your design requires if you may want to add more logic later in the design cycle, or to reserve logic and memory for on-chip debugging.
- Consider requirements for types of dedicated logic blocks, such as memory blocks of different sizes, or digital signal processing (DSP) blocks to implement certain arithmetic functions.
3.3.1. Device Migration Planning
Selecting a migration device impacts pin placement because some pins may serve different functions in different device densities or package sizes. If you make pin assignments in the Intel® Quartus® Prime software, the Pin Migration View in the Pin Planner highlights pins that change function between your migration devices.
3.4. Plan for Intellectual Property Cores
For IP cores that require additional license for production use, the Intel® FPGA IP Evaluation Mode, allows you to program the FPGA to verify the IP in the hardware before you purchase the IP license. Refer to Introduction to Intel FPGA IP Cores for general information on using Intel® FPGA IP cores.
3.5. Plan for Standard Interfaces
You can use the Intel® Quartus® Prime Interface Planner to help you accurately plan constraints for design implementation. Use Interface Planner to prototype interface implementations and rapidly define a legal device floorplan.
Standard interfaces simplify the interface logic to each design block, and enable individual team members to test their individual design blocks against the specification for the interface protocol to ease system integration.You can use the Intel® Quartus® Prime Platform Designer system integration tool to use standard interfaces and speed-up system-level integration. Platform Designer components use Avalon® standard interfaces for physical connections, allowing you to connect any logical device (either on-chip or off-chip) that has an Avalon® interface. Platform Designer allows you to define system components in a GUI, and then automatically generates the required interconnect logic, along with clock-crossing and width adapters.
The Avalon® standard includes two interface types:
- Avalon® memory-mapped—allow a component to use an address-mapped read or write protocol that connects master components to slave components.
- Avalon® streaming—enables point-to-point connections between streaming components that send and receive data using a high-speed, unidirectional system interconnect between source and sink ports.
3.6. Plan for Device Programming
You can define a configuration scheme on the Configuration tab of the Device and Pin Options dialog box. The Intel® Quartus® Prime software uses the settings for the configuration scheme, configuration device, and configuration device voltage to enable the appropriate dual purpose pins as regular I/O pins after you complete configuration. The Intel® Quartus® Prime software performs voltage compatibility checks of those pins during compilation of your design.
The technical documentation for each device family describes the available configuration options.
3.7. Plan for Device Power Consumption
Power estimation and analysis helps you ensure that your design satisfies thermal and power supply requirements:
- Thermal—ensure that the cooling solution is sufficient to dissipate the heat generated by the device. The computed junction temperature must fall within normal device specifications.
- Power supply—ensure that the power supplies provide adequate current to support device operation.
Early Power Estimator (EPE) Spreadsheet
The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization for your design. Estimating power consumption early in the design cycle allows planning of power budgets and avoids unexpected results when designing the PCB.
You can manually enter data into the EPE spreadsheet, or use the Intel® Quartus® Prime software to generate device resource information for your design.
To manually enter data into the EPE spreadsheet, enter the device resources, operating frequency, toggle rates, and other parameters for your design. If you do not have an existing design, estimate the number of device resources used in your design, and then enter the data into the EPE spreadsheet manually.
If you have an existing design or a partially completed design, you can use the Intel® Quartus® Prime software to generate the Early Power Estimator File (.txt, .csv) to assist you in completing the EPE spreadsheet.
The EPE spreadsheet includes the Import Data macro that parses the information in the EPE File and transfers the information into the spreadsheet. If you do not want to use the macro, you can manually transfer the data into the EPE spreadsheet. For example, after importing the EPE File information into the EPE spreadsheet, you can add device resource information. If the existing Intel® Quartus® Prime project represents only a portion of your full design, manually enter the additional device resources you use in the final design.
Intel® Quartus® Prime Power Analyzer
After you complete your design, you can use the Intel® Quartus® Prime Power Analyzer to perform a complete post-fit power analysis to check the power consumption more accurately. The Power Analyzer provides an accurate estimation of power, ensuring that thermal and supply limitations are met.
3.8. Plan for Interface I/O Pins
You can create a preliminary pin-out for an Intel FPGA with the Intel® Quartus® Prime Pin Planner before you develop the source code, based on standard I/O interfaces (such as memory and bus interfaces) and any other I/O requirements for your system.
The Intel® Quartus® Prime I/O Assignment Analysis checks that the pin locations and assignments are supported in the target FPGA architecture. You can then use I/O Assignment Analysis to validate I/O-related assignments that you create or modify throughout the design process. When you compile your design in the Intel® Quartus® Prime software, I/O Assignment Analysis runs automatically in the Fitter to validate that the assignments meet all the device requirements and generates error messages.
Early in the design process, before creating the source code, the system architect has information about the standard I/O interfaces (such as memory and bus interfaces), the IP cores in your design, and any other I/O-related assignments defined by system requirements. You can use this information with the Early Pin Planning feature in the Pin Planner to specify details about the design I/O interfaces. You can then create a top-level design file that includes all I/O information.
The Pin Planner interfaces with the IP core parameter editor, which allows you to create or import custom IP cores that use I/O interfaces. You can configure how to connect the functions and cores to each other by specifying matching node names for selected ports. You can create other I/O-related assignments for these interfaces or other design I/O pins in the Pin Planner, as described in this section. The Pin Planner creates virtual pin assignments for internal nodes, so internal nodes are not assigned to device pins during compilation.
You can use the I/O analysis results to change pin assignments or IP parameters even before you create your design, and repeat the checking process until the I/O interface meets your design requirements and passes the pin checks in the Intel® Quartus® Prime software. When you complete initial pin planning, you can create a revision based on the Intel® Quartus® Prime-generated netlist. You can then use the generated netlist to develop the top-level design file for your design, or disregard the generated netlist and use the generated Intel® Quartus® Prime Settings File (.qsf) with your design.
During this early pin planning, after you have generated a top-level design file, or when you have developed your design source code, you can assign pin locations and assignments with the Pin Planner.
With the Pin Planner, you can identify I/O banks, voltage reference (VREF) groups, and differential pin pairings to help you through the I/O planning process. If you selected a migration device, the Pin Migration View highlights the pins that have changed functions in the migration device when compared to the currently selected device. Selecting the pins in the Device Migration view cross-probes to the rest of the Pin Planner, so that you can use device migration information when planning your pin assignments. You can also configure board trace models of selected pins for use in “board-aware” signal integrity reports generated with the Enable Advanced I/O Timing option . This option ensures that you get accurate I/O timing analysis. You can use a Microsoft Excel spreadsheet to start the I/O planning process if you normally use a spreadsheet in your design flow, and you can export a Comma-Separated Value File (.csv) containing your I/O assignments for spreadsheet use when you assign all pins.
When you complete your pin planning, you can pass pin location information to PCB designers. The Pin Planner is tightly integrated with certain PCB design EDA tools, and can read pin location changes from these tools to check suggested changes. Your pin assignments must match between the Intel® Quartus® Prime software and your schematic and board layout tools to ensure the FPGA works correctly on the board, especially if you must make changes to the pin-out. The system architect uses the Intel® Quartus® Prime software to pass pin information to team members designing individual logic blocks, allowing them to achieve better timing closure when they compile their design.
Start FPGA planning before you complete the HDL for your design to improve the confidence in early board layouts, reduce the chance of error, and improve the overall time to market of the design. When you complete your design, use the Fitter reports for the final sign-off of pin assignments. After compilation, the Intel® Quartus® Prime software generates the Pin-Out File (.pin), and you can use this file to verify that each pin is correctly connected in board schematics.
3.8.1. Simultaneous Switching Noise Analysis
Intel provides tools for SSN analysis and estimation, including SSN characterization reports, an Early SSN Estimator (ESE) spreadsheet tool, and the SSN Analyzer in the Intel® Quartus® Prime software. SSN often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system. You must address SSN with estimation early in your system design, to minimize later board design changes. When your design is complete, verify your board design by performing a complete SSN analysis of your FPGA in the Intel® Quartus® Prime software.
3.9. Plan for other EDA Tools
3.9.1. Third-Party Synthesis Tools
Different synthesis tools may give different results for each design. To determine the best tool for your application, you can experiment by synthesizing typical designs for your application and coding style. Perform placement and routing in the Intel® Quartus® Prime software to get accurate timing analysis and logic utilization results.
The synthesis tool you choose may allow you to create an Intel® Quartus® Prime project and pass constraints, such as the EDA tool setting, device selection, and timing requirements that you specified in your synthesis project. You can save time when setting up your Intel® Quartus® Prime project for placement and routing.
Tool vendors frequently add new features, fix tool issues, and enhance performance for Intel devices, you must use the most recent version of third-party synthesis tools.
3.9.2. Third-Party Simulation Tools
Use the simulator version that your Intel® Quartus® Prime software version supports for best results. You must also use the model libraries provided with your Intel® Quartus® Prime software version. Libraries can change between versions, which might cause a mismatch with your simulation netlist.
3.10. Plan for On-Chip Debugging Tools
The Intel® Quartus® Prime in-system debugging tools offer different advantages and trade-offs, depending on the characteristics of your design. Consider the following debugging requirements when planning your design to support debugging tools:
- JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.
- Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic.
- Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging.
- Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which require I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required. Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation.
- Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core.
- Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually
connect the Signal Tap Logic Analyzer to
nodes in your design and ensure that the tapped node names do not change during
synthesis.
Table 9. Factors to Consider When Using Debugging Tools During Design Planning Stages Design Planning Factor Signal Tap Logic Analyzer
System Console In-System Memory Content Editor
Logic Analyzer Interface (LAI) Signal Probe In-System Sources and Probes
Virtual JTAG IP Core JTAG connections Yes Yes Yes Yes — Yes Yes Additional logic resources — Yes — — — — Yes Reserve device memory Yes Yes — — — — — Reserve I/O pins — — — Yes Yes — — Instantiate IP core in your HDL code — — — — — Yes Yes
3.11. Plan HDL Coding Styles
3.11.1. Design Recommendations
In a synchronous design, a clock signal triggers all events. When you meet all register timing requirements, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.
Clock signals have a large effect on the timing accuracy, performance, and reliability of your design. Problems with clock signals can cause functional and timing problems in your design. Use dedicated clock pins and clock routing for best results, and if you have PLLs in your target device, use the PLLs for clock inversion, multiplication, and division. For clock multiplexing and gating, use the dedicated clock control block or PLL clock switchover feature instead of combinational logic, if these features are available in your device. If you must use internally-generated clock signals, register the output of any combinational logic used as a clock signal to reduce glitches.
Consider the architecture of the device you choose so that you can use specific features in your design. For example, the control signals should use the dedicated control signals in the device architecture. Sometimes, you might need to limit the number of different control signals used in your design to achieve the best results.
3.11.2. Recommended HDL Coding Styles
If you design memory and DSP functions, you must understand the target architecture of your device so you can use the dedicated logic block sizes and configurations. Follow the coding guidelines for inferring Intel® FPGA IP and targeting dedicated device hardware, such as memory and DSP blocks.
3.11.3. Managing Metastability
Designers commonly use a synchronization chain to minimize the occurrence of metastable events. Ensure that your design accounts for synchronization between any asynchronous clock domains. Consider using a synchronizer chain of more than two registers for high-frequency clocks and frequently-toggling data signals to reduce the chance of a metastability failure.
You can use the Intel® Quartus® Prime software to analyze the average mean time between failures (MTBF) due to metastability when a design synchronizes asynchronous signals, and optimize your design to improve the metastability MTBF. The MTBF due to metastability is an estimate of the average time between instances when metastability could cause a design failure. A high MTBF (such as hundreds or thousands of years between metastability failures) indicates a more robust design. Determine an acceptable target MTBF given the context of your entire system and the fact that MTBF calculations are statistical estimates.
The Intel® Quartus® Prime software can help you determine whether you have enough synchronization registers in your design to produce a high enough MTBF at your clock and data frequencies.
3.12. Plan for Hierarchical and Team-Based Designs
3.12.1. Flat Compilation without Design Partitions
Although the source code may be hierarchical, the Compiler flattens and synthesizes all the design logic. Whenever you re-compile the project, the Compiler re-performs all available logic and placement optimizations on the entire design.
The flat compilation flow does not require any planning for design partitions. However, because the Intel® Quartus® Prime software recompiles the entire design whenever you change your design, flat design practices may require more overall compilation time for large designs. Additionally, you may find that the results for one part of the design change when you change a different part of your design. You can run Rapid Recompile to preserve portions of previous placement and routing in subsequent compilations. Rapid Recompile can reduce your compilation time in a flat or partitioned design when you make small changes to your design.
3.13. Design Planning Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 |
|
2018.05.07 | 18.0 | Initial release as separate chapter of Getting Started User Guide. |
Date | Version | Changes |
---|---|---|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.03 | 16.0.0 | Added information about Development Kit selection. |
2015.11.02 | 15.1.0 |
|
2015.05.04 | 15.0.0 | Remove support for Early Timing Estimate feature. |
2014.06.30 | 14.0.0 | Updated document format. |
November 2013 | 13.1.0 | Removed HardCopy device information. |
November, 2012 | 12.1.0 | Update for changes to early pin planning feature |
June 2012 | 12.0.0 | Editorial update. |
November 2011 | 11.0.1 | Template update. |
May 2011 | 11.0.0 |
|
December 2010 | 10.1.0 |
|
July 2010 | 10.0.0 |
|
November 2009 | 9.1.0 |
|
March 2009 | 9.0.0 |
|
November 2008 | 8.1.0 |
|
May 2008 | 8.0.0 |
|
4. Introduction to Intel FPGA IP Cores
The Intel® Quartus® Prime software installation includes the Intel® FPGA IP library. Integrate optimized and verified Intel® FPGA IP cores into your design to shorten design cycles and maximize performance. The Intel® Quartus® Prime software also supports integration of IP cores from other sources. Use the IP Catalog (Tools > IP Catalog) to efficiently parameterize and generate synthesis and simulation files for your custom IP variation. The Intel® FPGA IP library includes the following types of IP cores:
- Basic functions
- DSP functions
- Interface protocols
- Low power functions
- Memory interfaces and controllers
- Processors and peripherals
This document provides basic information about parameterizing, generating, upgrading, and simulating stand-alone IP cores in the Intel® Quartus® Prime software.
4.1. IP Catalog and Parameter Editor
- Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
- Type in the Search field to locate any full or partial IP core name in IP Catalog.
- Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
- Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel® Quartus® Prime IP file (.ip) for an IP variation in Intel® Quartus® Prime Pro Edition projects.
4.1.1. The Parameter Editor
- Use the Presets window to apply preset parameter values for specific applications (for select cores).
- Use the Details window to view port and parameter descriptions, and click links to documentation.
- Click Generate > Generate Testbench System to generate a testbench system (for select cores).
- Click Generate > Generate Example Design to generate an example design (for select cores).
- Click Validate System Integrity to validate a system's generic components against companion files. (Platform Designer systems only)
- Click Sync All System Info to validate a system's generic components against companion files. (Platform Designer systems only)
The IP Catalog is also available in Platform Designer (View > IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Intel® Quartus® Prime IP Catalog. Refer to Creating a System with Platform Designer or Creating a System with Platform Designer for information on use of IP in Platform Designer and Platform Designer, respectively.
4.2. Installing and Licensing Intel FPGA IP Cores
The Intel® Quartus® Prime software installs IP cores in the following locations by default:
Location | Software | Platform |
---|---|---|
<drive>:\intelFPGA_pro\quartus\ip\altera | Intel® Quartus® Prime Pro Edition | Windows* |
<drive>:\intelFPGA\quartus\ip\altera | Intel® Quartus® Prime Standard Edition | Windows |
<home directory>:/intelFPGA_pro/quartus/ip/altera | Intel® Quartus® Prime Pro Edition | Linux* |
<home directory>:/intelFPGA/quartus/ip/altera | Intel® Quartus® Prime Standard Edition | Linux |
4.2.1. Intel FPGA IP Evaluation Mode
- Simulate the behavior of a licensed Intel® FPGA IP core in your system.
- Verify the functionality, size, and speed of the IP core quickly and easily.
- Generate time-limited device programming files for designs that include IP cores.
- Program a device with your IP core and verify your design in hardware.
Intel® FPGA IP Evaluation Mode supports the following operation modes:
- Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
- Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.
When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.
You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.
Intel® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center.
The Intel® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel® Quartus® Prime design software, and all unlicensed IP cores.
4.2.1.1. Intel FPGA IP Versioning
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
4.2.1.2. Checking the IP License Status
To generate and view the Assembler report in the GUI:
- Click Assembler on the Compilation Dashboard.
- When the Assembler (and any prerequisite stages of compilation) complete, click the Report icon for the Assembler in the Compilation Dashboard.
- Click the Encrypted IP Cores
Summary report.Encrypted IP Cores Summary Report
To generate and view the Assembler report at the command line:
- Type the following
command:
quartus_asm <project name> -c <project revision>
- View the output report in:
<project>/output_files/<project_name>.asm.rpt
Example of the assembler report: +----------------------------------------------------------------------+ ; Assembler Encrypted IP Cores Summary ; +--------+----------------------------------------------+--------------+ ; Vendor ; IP Core Name ; License Type ; +--------+----------------------------------------------+--------------+ ; Intel ; PCIe SRIOV with 4-PFs and 2K-VFs (6AF7 00FB) ; Unlicensed ; ; Intel ; Signal Tap (6AF7 BCE1) ; Licensed ; ; Intel ; Signal Tap (6AF7 BCEC) ; Licensed ; +--------+----------------------------------------------+--------------+
4.3. IP General Settings
The following settings control how the Intel® Quartus® Prime software manages IP cores in a project:
Setting | Description | Location |
---|---|---|
Maximum Platform Designer memory usage size | Increase if you experience slow processing for large systems, or for out of memory errors. |
Tools > Options > IP Settings
Or Tasks pane > Settings > IP Settings |
IP generation HDL preference | The parameter editor generates the HDL you specify for IP variations. | |
IP Regeneration Policy | Controls when synthesis files regenerate for each IP variation. Typically, you Always regenerate synthesis files for IP cores after making changes to an IP variation. | |
Generate IP simulation model when generating IP | Enables automatic generation of simulation models every time you generate the IP. | |
Use available processors for parallel generation of Quartus project IPs | Directs Platform Designer to generate IPs in parallel, using the number of processors that you specify in the Compilation Process Settings pane of the Intel® Quartus® Prime project settings. | |
Additional project and global IP search locations. The Intel® Quartus® Prime software searches for IP cores in the project directory, in the Intel® Quartus® Prime installation directory, and in the IP search path. |
Tools > Options > IP Catalog Search
Locations
Or Tasks pane > Settings > IP Catalog Search Locations |
4.4. Adding Your Own IP to IP Catalog
Follow these steps to add custom or third-party IP to the IP Catalog:
- In the Intel® Quartus® Prime software, click Tools > Options > IP Search Path) to open the IP Search Path Options dialog box.
- Click Add or Remove to add/remove a location that contains IP.
-
To refresh the IP Catalog, click Refresh IP Catalog in the
Intel®
Quartus® Prime
Platform Designer, or click File > Refresh Systemin Platform Designer.
Figure 42. Refreshing IP Catalog
4.5. Best Practices for Intel FPGA IP
- Do not manually edit or write your own .qsys, .ip, or .qip file. Use the
Intel®
Quartus® Prime software tools to create and
edit these files.Note: When generating IP cores, do not generate files into a directory that has a space in the directory name or path. Spaces are not legal characters for IP core paths or names.
- When you generate an IP core using the IP Catalog, the Intel® Quartus® Prime software generates a .qsys (for Platform Designer-generated IP cores) or a .ip file (for Intel® Quartus® Prime Pro Edition) or a .qip file. The Intel® Quartus® Prime Pro Edition software automatically adds the generated .ip to your project. In the Intel® Quartus® Prime Standard Edition software, add the .qip to your project. Do not add the parameter editor generated file (.v or .vhd) to your design without the .qsys or .qip file. Otherwise, you cannot use the IP upgrade or IP parameter editor feature.
- Plan your directory structure ahead of time. Do not change the relative path between a .qsys file and it's generation output directory. If you must move the .qsys file, ensure that the generation output directory remains with the .qsys file.
- Do not add IP core files directly from the /quartus/libraries/megafunctions directory in your project. Otherwise, you must update the files for each subsequent software release. Instead, use the IP Catalog and then add the .qip to your project.
- Do not use IP files that the Intel® Quartus® Prime software generates for RAM or FIFO blocks targeting older device families (even though the Intel® Quartus® Prime software does not issue an error). The RAM blocks that Intel® Quartus® Prime generates for older device families are not optimized for the latest device families.
- When generating a ROM function, save the resulting .mif or .hex file in the same folder as the corresponding IP core's .qsys or .qip file. For example, moving all of your project's .mif or .hex files to the same directory causes relative path problems after archiving the design.
- Always use the Intel® Quartus® Prime ip-setup-simulation and ip-make-simscript utilities to generate simulation scripts for each IP core or Platform Designer system in your design. These utilities produce a single simulation script that does not require manual update for upgrades to Intel® Quartus® Prime software or IP versions, as Simulating Intel FPGA IP Cores describes.
4.6. Generating IP Cores ( Intel Quartus Prime Pro Edition)
Follow these steps to locate, instantiate, and customize an IP core in the parameter editor:
- Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
-
Specify a top-level name for your custom IP variation. Do not
include spaces in IP variation names or paths. The parameter editor saves the IP
variation settings in a file named
<your_ip>
.ip. Click OK. The parameter editor appears.
Figure 43. IP Parameter Editor ( Intel® Quartus® Prime Pro Edition)
-
Set the parameter values in the parameter editor and view the
block diagram for the component. The Parameterization Messages tab at the bottom displays any errors
in IP parameters:
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core parameters. - Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
-
After generating
and instantiating your IP variation, make appropriate pin assignments to
connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
4.6.1. IP Core Generation Output ( Intel Quartus Prime Pro Edition)
File Name | Description |
---|---|
<your_ip>.ip | Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file. |
<your_ip>.cmp | The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files. |
<your_ip>_generation.rpt | IP or Platform Designer generation log file. Displays a summary of the messages during IP generation. |
<your_ip>.qgsimc (Platform Designer systems only) | Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qgsynth (Platform Designer systems only) | Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.csv | Contains information about the upgrade status of the IP component. |
<your_ip>.bsf | A symbol representation of the IP variation for use in Block Diagram Files (.bdf). |
<your_ip>.spd | Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize. |
<your_ip>.ppf | The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. |
<your_ip>_bb.v | Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox. |
<your_ip>_inst.v or _inst.vhd | HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation. |
<your_ip>.regmap | If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console. |
<your_ip>.svd |
Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name. |
<your_ip>.v <your_ip>.vhd |
HDL files that instantiate each submodule or child IP core for synthesis or simulation. |
mentor/ | Contains a msim_setup.tcl script to set up and run a ModelSim* simulation. |
aldec/ | Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS* MX simulation. |
/cadence | Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSim simulation. |
/xcelium | Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation. |
/submodules | Contains HDL files for the IP core submodule. |
<IP submodule>/ | Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. |
4.6.2. Scripting IP Core Generation
-
Run qsys-script to start a Tcl script that instantiates the IP and sets parameters:
qsys-script --script=<script_file>.tcl
-
Run qsys-generate to generate the IP core variation:
qsys-generate <IP variation file>.qsys
4.7. Modifying an IP Variation
Menu Command | Action |
---|---|
File > Open | Select the top-level HDL (.v, or .vhd) IP variation file to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
View > Project Navigator > IP Components | Double-click the IP variation to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
Project > Upgrade IP Components | Select the IP variation and click Upgrade in Editor to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
4.8. Upgrading IP Cores
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for an IP variation in the project. Upgrade IP variations that require upgrade before compilation in the current version of the Intel® Quartus® Prime software.
IP Core Status | Description |
---|---|
IP Upgraded ![]() |
Indicates that your IP variation uses the latest version of the Intel® FPGA IP core. |
IP Component Outdated ![]() |
Indicates that your IP variation uses an outdated version of the IP core. |
IP End of Life ![]() |
Indicates that Intel designates the IP core as end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in future releases of the Intel® Quartus® Prime software. |
IP Upgrade Mismatch Warning ![]() |
Provides warning of non-critical IP core differences in migrating IP to another device family. |
IP has incompatible subcores![]() |
Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation, because the IP has incompatible subcores |
Compilation of IP Not Supported ![]() |
Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation. This can occur if another edition of the Intel® Quartus® Prime software, such as the Intel® Quartus® Prime Standard Edition, generated this IP. Replace this IP component with a compatible component in the current edition. |
Follow these steps to upgrade IP cores:
-
In the latest version of the
Intel®
Quartus® Prime software, open the
Intel®
Quartus® Prime project containing an outdated IP core variation. The
Upgrade IP Components dialog box
automatically displays the status of IP cores in your project, along with
instructions for upgrading each core. To access this dialog box manually, click
Project > Upgrade IP Components.
- To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP cores, and click Auto Upgrade. The Status and Version columns update when upgrade is complete. Example designs that any Intel® FPGA IP core provides regenerate automatically whenever you upgrade an IP core.
-
To manually upgrade an individual IP core, select the IP core
and click Upgrade in Editor (or simply
double-click the IP core name). The parameter editor opens, allowing you to
adjust parameters and regenerate the latest version of the IP core.
Figure 46. Upgrading IP Cores
Note: Intel® FPGA IP cores older than Intel® Quartus® Prime software version 12.0 do not support upgrade. Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous two versions of each IP core. The Intel® FPGA IP Core Release Notes reports any verification exceptions for Intel® FPGA IP cores. Intel does not verify compilation for IP cores older than the previous two releases.
4.8.1. Upgrading IP Cores at Command-Line
- To upgrade a single IP core at the command-line, type the following command:
quartus_sh –ip_upgrade –variation_files <my_ip>.<qsys,.v, .vhd> \ <quartus_project> Example: quartus_sh -ip_upgrade -variation_files mega/pll25.qsys hps_testx
- To simultaneously upgrade multiple IP cores at the command-line, type the
following command:
quartus_sh –ip_upgrade –variation_files “<my_ip1>.<qsys,.v, .vhd>> \ ; <my_ip_filepath/my_ip2>.<hdl>” <quartus_project> Example: quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.qsys;mega/pll3.qsys" hps_testx
4.8.2. Migrating IP Cores to a Different Device
- To display the IP cores that require migration, click Project > Upgrade IP Components. The Description field provides migration instructions and version differences.
- To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP cores, and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete.
- To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family.
- Click Generate HDL, and confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format.
- Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files. The Device Family column displays the new target device name when migration is complete.
-
To ensure correctness, review the latest parameters in the
parameter editor or generated HDL.
Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip> .bsf. Migration of some IP cores requires installed support for the original and migration device families.
4.8.3. Troubleshooting IP or Platform Designer System Upgrade
Upgrade IP Components Field | Description |
---|---|
Status | Displays the "Success" or "Failed" status of each upgrade or migration. Click the status of any upgrade that fails to open the IP Upgrade Report. |
Version | Dynamically updates the version number when upgrade is successful. The text is red when the IP requires upgrade. |
Device Family | Dynamically updates to the new device family when migration is successful. The text is red when the IP core requires upgrade. |
Auto Upgrade | Runs automatic upgrade on all IP cores that support auto upgrade. Also, automatically generates a <Project Directory> /ip_upgrade_port_diff_report report for IP cores or Platform Designer systems that fail upgrade. Review these reports to determine any port differences between the current and previous IP core version. |
- If the current version of the software does not support the IP variant, right-click the component and click Remove IP Component from Project. Replace this IP core or Platform Designer system with the one supported in the current version of the software.
- If the current target device does not support the IP variant, select a supported device family for the project, or replace the IP variant with a suitable replacement that supports your target device.
- If an upgrade or migration fails, click Failed in the Status field to display and review details of the IP Upgrade Report. Click the Release Notes link for the latest known issues about the IP core. Use this information to determine the nature of the upgrade or migration failure and make corrections before upgrade.
- Run Auto Upgrade to automatically generate an IP Ports Diff report for each IP core or Platform Designer system that fails upgrade. Review the reports to determine any port differences between the current and previous IP core version. Click Upgrade in Editor to make specific port changes and regenerate your IP core or Platform Designer system.
- If your IP core or Platform Designer system does not support Auto Upgrade, click Upgrade in Editor to resolve errors and regenerate the component in the parameter editor.
4.9. Simulating Intel FPGA IP Cores
The Intel® Quartus® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you choose, IP core simulation involves the following steps:
- Generate simulation model, testbench (or example design), and simulator setup script files.
- Set up your simulator environment and any simulation scripts.
- Compile simulation model libraries.
- Run your simulator.
4.9.1. Generating IP Simulation Files
- To specify your supported simulator and options for IP simulation file generation, click Assignment > Settings > EDA Tool Settings > Simulation.
- To parameterize a new IP variation, enable generation of simulation files, and generate the IP core synthesis and simulation files, click Tools > IP Catalog.
- To edit parameters and regenerate synthesis or simulation files for an existing IP core variation, click View > Project Navigator > IP Components.
File Type | Description | File Name |
---|---|---|
Simulator setup scripts | Vendor-specific scripts to compile, elaborate, and simulate Intel® FPGA IP models and simulation model library files. |
<my_dir>/aldec/riviera_setup.tcl <my_dir>/cadence/ncsim__setup.sh <my_dir>/xcelium/xcelium_setup.sh <my_dir>/mentor/msim_setup.tcl <my_dir>/synopsys/vcs/vcs_setup.sh <my_dir>/synopsys/vcsmx/vcsmx_setup.sh |
4.9.2. Scripting IP Simulation
- Click Project > Upgrade IP Components > Generate Simulator Script for IP (or run the ip-setup-simulation utility) to generate or regenerate a combined simulator setup script for all IP for each simulator.
-
Use the templates in the generated script to source the
combined script in your top-level simulation script. Each simulator's combined
script file contains a rudimentary template that you adapt for integration of
the setup script into a top-level simulation script.
This technique eliminates manual update of simulation scripts if you modify or upgrade the IP variation.
4.9.2.1. Generating a Combined Simulator Setup Script ( Intel Quartus Prime Pro Edition)
Source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:
- IP core initial generation or regeneration with new parameters
- Intel® Quartus® Prime software version upgrade
- IP core version upgrade
- Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP Cores or Upgrading IP Cores.
- Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
-
To incorporate the generated simulator setup script into your top-level simulation script, refer to the template
section in the generated simulator setup script as a guide to creating a top-level script:
- Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
- Remove the comments at the beginning of each line from the copied template sections.
-
Specify the customizations you require to match your design simulation requirements, for example:
- Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
- If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
- Compile the top-level HDL file (for example, a test program) and all other files in the design.
- Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
-
Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.
Table 17. Simulation Script Utilities Utility Syntax ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible. ip-setup-simulation --quartus-project=<my proj> --output-directory=<my_dir> --use-relative-paths --compile-to-work
--use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.
ip-make-simscript generates a combined simulation script for all IP cores that you specify on the command line. Specify one or more .spd files and an output directory in the command. Running the script compiles IP simulation models into various simulation libraries. ip-make-simscript --spd=<ipA.spd,ipB.spd> --output-directory=<directory>
ip-make-simscript generates a combined simulation script for all IP cores and subsystems that you specify on the command line. ip-make-simscript --system-files=<ipA.ip, ipB.ip> --output-directory=<directory>
Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and paste these
lines into a new file. For example, sim_top.tcl.
# # Start of template # # If the copied and modified template file is "aldec.do", run it as: # # vsim -c -do aldec.do # # # # Source the generated sim script # source rivierapro_setup.tcl # # Compile eda/sim_lib contents first # dev_com # # Override the top-level name (so that elab is useful) # set TOP_LEVEL_NAME top # # Compile the standalone IP. # com # # Compile the top-level # vlog -sv2k5 ../../top.sv # # Elaborate the design. # elab # # Run the simulation # run # # Report success to the shell # exit -code 0 # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "aldec.do", run it as: # vsim -c -do aldec.do # # Source the generated sim script source rivierapro_setup.tcl # Compile eda/sim_lib contents first dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME top # Compile the standalone IP. com # Compile the top-level vlog -sv2k5 ../../top.sv # Elaborate the design. elab # Run the simulation run # Report success to the shell exit -code 0 # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog –sv2k5 ../../sim_top.sv
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
-
Run the new top-level script from the generated simulation directory:
vsim –c –do <path to sim_top>.tcl
Sourcing Cadence Incisive* Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example,
ncsim.sh.
# # Start of template # # If the copied and modified template file is "ncsim.sh", run it as: # # ./ncsim.sh # # # # Do the file copy, dev_com and com steps # source ncsim_setup.sh # SKIP_ELAB=1 # SKIP_SIM=1 # # # Compile the top level module # ncvlog -sv "$QSYS_SIMDIR/../top.sv" # # # Do the elaboration and sim steps # # Override the top-level name # # Override the sim options, so the simulation # # runs forever (until $finish()). # source ncsim_setup.sh # SKIP_FILE_COPY=1 # SKIP_DEV_COM=1 # SKIP_COM=1 # TOP_LEVEL_NAME=top # USER_DEFINED_SIM_OPTIONS="" # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "ncsim.sh", run it as: # ./ncsim.sh # # Do the file copy, dev_com and com steps source ncsim_setup.sh SKIP_ELAB=1 SKIP_SIM=1 # Compile the top level module ncvlog -sv "$QSYS_SIMDIR/../top.sv" # Do the elaboration and sim steps # Override the top-level name # Override the sim options, so the simulation # runs forever (until $finish()). source ncsim_setup.sh SKIP_FILE_COPY=1 SKIP_DEV_COM=1 SKIP_COM=1 TOP_LEVEL_NAME=top USER_DEFINED_SIM_OPTIONS="" # End of template
-
Modify the TOP_LEVEL_NAME and
compilation step appropriately, depending on the simulation’s top-level file.
For example:
TOP_LEVEL_NAME=sim_top \ ncvlog -sv "$QSYS_SIMDIR/../top.sv"
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to ncsim.sh.
Sourcing Cadence Xcelium* Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and paste these lines into a new file.
For example, xmsim.sh.
# #Start of template # # Xcelium Simulation Script. # # If the copied and modified template file is "xmsim.sh", run it as: # # ./xmsim.sh # # # # Do the file copy, dev_com and com steps # source <script generation output directory>/xcelium/xcelium_setup.sh \ # SKIP_ELAB=1 \ # SKIP_SIM=1 \ # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \ # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your # design> \ # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for # your design> \ # QSYS_SIMDIR=<script generation output directory> # # # # Compile all design files and testbench files, including the top level. # # (These are all the files required for simulation other than the files # # compiled by the IP script) # # # xmvlog <compilation options> <design and testbench files> # # # # TOP_LEVEL_NAME is used in this script to set the top-level simulation # # or testbench module/entity name. # # # # Run the IP script again to elaborate and simulate the top level: # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". # # # source <script generation output directory>/xcelium/xcelium_setup.sh \ # SKIP_FILE_COPY=1 \ # SKIP_DEV_COM=1 \ # SKIP_COM=1 \ # TOP_LEVEL_NAME=<simulation top> \ # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \ # USER_DEFINED_SIM_OPTIONS=<simulation options for your design> # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # Xcelium Simulation Script (Beta Version). # If the copied and modified template file is "xmsim.sh", run it as: # ./xmsim.sh # # Do the file copy, dev_com and com steps source <script generation output directory>/xcelium/xcelium_setup.sh \ SKIP_ELAB=1 \ SKIP_SIM=1 \ USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \ USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \ USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \ QSYS_SIMDIR=<script generation output directory> # # Compile all design files and testbench files, including the top level. # (These are all the files required for simulation other than the files # compiled by the IP script) # xmvlog <compilation options> <design and testbench files> # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or # testbench module/entity name. # # Run the IP script again to elaborate and simulate the top level: # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS. # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". # source <script generation output directory>/xcelium/xcelium_setup.sh \ SKIP_FILE_COPY=1 \ SKIP_DEV_COM=1 \ SKIP_COM=1 \ TOP_LEVEL_NAME=<simulation top> \ USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \ USER_DEFINED_SIM_OPTIONS=<simulation options for your design> # End of template
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to xmsim.sh.
Sourcing Mentor Graphics ModelSim* Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example,
sim_top.tcl.
# # Start of template # # If the copied and modified template file is "mentor.do", run it # # as: vsim -c -do mentor.do # # # # Source the generated sim script # source msim_setup.tcl # # Compile eda/sim_lib contents first # dev_com # # Override the top-level name (so that elab is useful) # set TOP_LEVEL_NAME top # # Compile the standalone IP. # com # # Compile the top-level # vlog -sv ../../top.sv # # Elaborate the design. # elab # # Run the simulation # run -a # # Report success to the shell # exit -code 0 # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "mentor.do", run it # as: vsim -c -do mentor.do # # Source the generated sim script source msim_setup.tcl # Compile eda/sim_lib contents first dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME top # Compile the standalone IP. com # Compile the top-level vlog -sv ../../top.sv # Elaborate the design. elab # Run the simulation run -a # Report success to the shell exit -code 0 # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog -sv ../../sim_top.sv
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
-
Run the resulting top-level script from the generated simulation
directory:
vsim –c –do <path to sim_top>.tcl
Sourcing Synopsys VCS* Simulator Setup Scripts
-
The generated simulation script contains these template lines. Cut and paste
the lines preceding the “helper file” into a new executable file. For example,
synopsys_vcs.f.
# # Start of template # # If the copied and modified template file is "vcs_sim.sh", run it # # as: ./vcs_sim.sh # # # # Override the top-level name # # specify a command file containing elaboration options # # (system verilog extension, and compile the top-level). # # Override the sim options, so the simulation # # runs forever (until $finish()). # source vcs_setup.sh # TOP_LEVEL_NAME=top # USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" # USER_DEFINED_SIM_OPTIONS="" # # # helper file: synopsys_vcs.f # +systemverilogext+.sv # ../../../top.sv # # End of template
-
Delete the first two characters of each line (comment and space) for the
vcs.sh file, as shown below:
# Start of template # If the copied and modified template file is "vcs_sim.sh", run it # as: ./vcs_sim.sh # # Override the top-level name # specify a command file containing elaboration options # (system verilog extension, and compile the top-level). # Override the sim options, so the simulation # runs forever (until $finish()). source vcs_setup.sh TOP_LEVEL_NAME=top USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" USER_DEFINED_SIM_OPTIONS=""
-
Delete the first two characters of each line (comment and space) for the
synopsys_vcs.f file, as shown below:
# helper file: synopsys_vcs.f +systemverilogext+.sv ../../../top.sv # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
TOP_LEVEL_NAME=sim_top
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to vcs_sim.sh.
Sourcing Synopsys VCS MX Simulator Setup Scripts
-
The generated simulation script contains these template lines. Cut and paste
the lines preceding the “helper file” into a new executable file. For example,
vcsmx.sh.
# # Start of template # # If the copied and modified template file is "vcsmx_sim.sh", run # # it as: ./vcsmx_sim.sh # # # # Do the file copy, dev_com and com steps # source vcsmx_setup.sh # SKIP_ELAB=1 # SKIP_SIM=1 # # # Compile the top level module vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" # # Do the elaboration and sim steps # # Override the top-level name # # Override the sim options, so the simulation runs # # forever (until $finish()). # source vcsmx_setup.sh # SKIP_FILE_COPY=1 # SKIP_DEV_COM=1 # SKIP_COM=1 # TOP_LEVEL_NAME="'-top top'" # USER_DEFINED_SIM_OPTIONS="" # # End of template
-
Delete the first two characters of each line (comment and space), as shown
below:
# Start of template # If the copied and modified template file is "vcsmx_sim.sh", run # it as: ./vcsmx_sim.sh # # Do the file copy, dev_com and com steps source vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1 # Compile the top level module vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" # Do the elaboration and sim steps # Override the top-level name # Override the sim options, so the simulation runs # forever (until $finish()). source vcsmx_setup.sh SKIP_FILE_COPY=1 SKIP_DEV_COM=1 SKIP_COM=1 TOP_LEVEL_NAME="'-top top'" USER_DEFINED_SIM_OPTIONS="" # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
TOP_LEVEL_NAME=”-top sim_top’”
-
Make the appropriate changes to the compilation of the your top-level file, for
example:
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to vcsmx_sim.sh.
4.10. Synthesizing IP Cores in Other EDA Tools
The area and timing estimation netlist describes the IP core connectivity and architecture, but does not include details about the true functionality. This information enables certain third-party synthesis tools to better report area and timing estimates. In addition, synthesis tools can use the timing information to achieve timing-driven optimizations and improve the quality of results.
The Intel® Quartus® Prime software generates the <variant name>_syn.v netlist file in Verilog HDL format, regardless of the output file format you specify. If you use this netlist for synthesis, you must include the IP core wrapper file <variant name> .v or <variant name> .vhd in your Intel® Quartus® Prime project.
4.11. Instantiating IP Cores in HDL
4.11.1. Example Top-Level Verilog HDL Module
module MF_top (a, b, sel, datab, clock, result); input [31:0] a, b, datab; input clock, sel; output [31:0] result; wire [31:0] wire_dataa; assign wire_dataa = (sel)? a : b; altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result)); defparam inst1.pipeline = 11, inst1.width_exp = 8, inst1.width_man = 23, inst1.exception_handling = "no"; endmodule
4.11.2. Example Top-Level VHDL Module
library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.altera_mf_components.all; entity MF_top is port (clock, sel : in std_logic; a, b, datab : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0)); end entity; architecture arch_MF_top of MF_top is signal wire_dataa : std_logic_vector(31 downto 0); begin wire_dataa <= a when (sel = '1') else b; inst1 : altfp_mult generic map ( pipeline => 11, width_exp => 8, width_man => 23, exception_handling => "no") port map ( dataa => wire_dataa, datab => datab, clock => clock, result => result); end arch_MF_top;
4.12. Support for the IEEE 1735 Encryption Standard
The encryption key is the same for Verilog HDL and VHDL. You can pass parameters to the instantiation of an encrypted module using the same method as a non-encrypted module.
Type encrypt_1735 --help at the Intel® Quartus® Prime command line to view syntax and all supported options for the encrypt_1735 utility.
encrypt_1735 [-h | --help[=<option|topic>] | -v] encrypt_1735 <other options> Options: -------- -? -f <argument file> -h --256_bit[=<value>] --help[=<option|topic>] --language=<verilog | systemverilog| vhdl> --lower_priority --of=<some_file> --quartus --simulation[=<aldec | cadence | mentor | synopsys (comma delimited)>] --tcl_jou_file=<[tcl_jou_filename=]on|off> --tcl_log_file=<[tcl_log_filename=]on|off>
Adding the following Verilog or VHDL pragma to your RTL, along with the public key, enables the Intel® Quartus® Prime software to use the key to decrypt IP core files.
Verilog/SystemVerilog Encryption Pragma (Third-Party Tools):
`pragma protect key_keyowner="Intel Corporation" `pragma protect data_method="aes128-cbc" `pragma protect key_method="rsa" `pragma protect key_keyname="Intel-FPGA-Quartus-RSA-1" `pragma protect key_public_key <encrypted session key> `pragma protect begin `pragma protect end
VHDL Encryption Pragma (Third-Party Tools):
`protect key_keyowner = “Intel Corporation” `protect data_method="aes128-cbc" `protect key_method = “rsa” `protect key_keyname = “Intel-FPGA-Quartus-RSA-1” `protect key_block <Encrypted session key>
Only file encryption with a third-party tool requires the public encryption key. File encryption with the Intel® Quartus® Prime Pro Edition software does not require the public encryption key.
Use one of the following methods to obtain the public encryption key:
- To obtain the encryption key, login or register for a My-Intel account, and then submit an Intel® Premier Support case requesting the encryption key.
- If you are ineligible for Intel® Premier Support, you can submit a question regarding the "IEEE 1735 Encryption Public Key" to the Intel® Community Forum for assistance.
4.13. Introduction to Intel FPGA IP Cores Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.09.30 | 19.3.0 |
|
2019.05.13 | 18.1.0 |
|
2018.10.24 | 18.1.0 |
|
2018.09.24 | 18.1.0 |
|
2018.05.07 | 18.0.0 |
|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2018.05.07 | 18.0 | Initial release as separate chapter of Getting Started User Guide. |
5. Migrating to Intel Quartus Prime Pro Edition
Migrating to Intel® Quartus® Prime Pro Edition requires the following changes to other Quartus software product projects:
- Upgrade project assignments and constraints with equivalent Intel® Quartus® Prime Pro Edition assignments.
- Upgrade all Intel® FPGA IP core variations and Platform Designer systems in your project.
- Upgrade design RTL to standards-compliant VHDL, Verilog HDL, or SystemVerilog.
This document describes each migration step in detail.
5.1. Keep Pro Edition Project Files Separate
Intel® Quartus® Prime Pro Edition projects do not support compilation in other Quartus software products, and vice versa. The Intel® Quartus® Prime Pro Edition software generates an error if the Compiler detects other Quartus software product's features in project files.
Before migrating other Quartus software product projects, click Project > Archive Project to save a copy of your original project before making modifications for migration.
5.2. Upgrade Project Assignments and Constraints
The following sections detail each type project assignment upgrade that migration requires.
5.2.1. Modify Entity Name Assignments
- "a_entity:a|b_entity:b|c_entity:c" (includes deprecated entity names)
- “a|b|c” (omits deprecated entity names)
While the current version of the Intel® Quartus® Prime Pro Edition software still accepts entity names in the .qsf, the Compiler ignores the entity name. The Compiler generates a warning message upon detection of an entity names in the .qsf. Whenever possible, you should remove entity names from assignments, and discontinue reliance on entity-based assignments. Future versions of the Intel® Quartus® Prime Pro Edition software may eliminate all support for entity-based assignments.
5.2.2. Resolve Timing Constraint Entity Names
Use .sdc files from other Quartus software products without modification. However, any scripts that include custom processing of names that the .sdc command returns, such as get_registers may require modification. Your scripts must reflect that returned strings do not include entity names.
The .sdc commands respect wildcard patterns containing entity names. Review the Timing Analyzer reports to verify application of all constraints. The following example illustrates differences between functioning and non-functioning .sdc scripts:
# Apply a constraint to all registers named "acc" in the entity "counter". # This constraint functions in both SE and PE, because the SDC # command always understands wildcard patterns with entity names in them set_false_path –to [get_registers “counter:*|*acc”] # This does the same thing, but first it converts all register names to # strings, which includes entity names by default in the SE # but excludes them by default in the PE. The regexp will therefore # fail in PE by default. # # This script would also fail in the SE, and earlier # versions of Quartus II, if entity name display had been disabled # in the QSF. set all_reg_strs [query_collection –list –all [get_registers *]] foreach keeper $all_reg_strs { if {[regexp {counter:*|:*acc} $keeper]} { set_false_path –to $keeper } }Removal of the entity name processing from .sdc files may not be possible due to complex processing involving node names. Use standard .sdc whenever possible to replace such processing. Alternatively, add the following code to the top and bottom of your script to temporarily re-enable entity name display in the .sdc file:
# This script requires that entity names be included # due to custom name processing set old_mode [set_project_mode -get_mode_value always_show_entity_name] set_project_mode -always_show_entity_name on <... the rest of your script goes here ...> # Restore the project mode set_project_mode -always_show_entity_name $old_mode
5.2.3. Verify Generated Node Name Assignments
Avoid dependence on synthesis-generated names due to frequent changes in name generation. In addition, verify the names of duplicated registers and PLL clock outputs to ensure compatibility with any script or constraint.
5.2.4. Replace Logic Lock (Standard) Regions
-
Edit the .qsf to delete
or comment out all of the following Logic Lock assignments:
set_global_assignment -name LL_ENABLED* set_global_assignment -name LL_AUTO_SIZE* set_global_assignment -name LL_STATE FLOATING* set_global_assignment -name LL_RESERVED* set_global_assignment -name LL_CORE_ONLY* set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE* set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT* set_global_assignment -name LL_PR_REGION* set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE* set_global_assignment -name LL_WIDTH* set_global_assignment -name LL_HEIGHT set_global_assignment -name LL_ORIGIN set_instance_assignment -name LL_MEMBER_OF
-
Edit the .qsf or click
Tools > Chip Planner to define new Logic Lock
regions. Logic Lock constraint syntax is
simplified, for example:
set_instance_assignment -name PLACE_REGION "1 1 20 20" -to fifo1 set_instance_assignment -name RESERVE_PLACE_REGION OFF -to fifo1 set_instance_assignment -name CORE_ONLY_PLACE_REGION OFF -to fifo1
Compilation fails if synthesis finds other Quartus software product's Logic Lock assignments in an Intel® Quartus® Prime Pro Edition project. The following table compares other Quartus software product region constraint support with the Intel® Quartus® Prime Pro Edition software.
Table 18. Region Constraints Per Edition Constraint Type Logic Lock (Standard) Region Support Other Quartus Software Products
Logic Lock Region Support Intel® Quartus® Prime Pro Edition
Fixed rectangular, nonrectangular or non-contiguous regions Full support. Full support. Chip Planner entry Full support. Full support. Periphery element assignments Supported in some instances. Full support. Use “core-only” regions to exclude the periphery. Nested (“hierarchical”) regions Supported but separate hierarchy from the user instance tree. Supported in same hierarchy as user instance tree. Reserved regions Limited support for nested or nonrectangular reserved regions. Reserved regions typically cannot cross I/O columns; use non-contiguous regions instead. Full support for nested and nonrectangular regions. Reserved regions can cross I/O columns without affecting periphery logic if the regions are "core-only". Routing regions Limited support via “routing expansion.” No support with hierarchical regions. Full support (including future support for hierarchical regions). Floating or autosized regions Full support. No support. Region names Regions have names. Regions are identified by the instance name of the constrained logic. Multiple instances in the same region Full support. Support for non-reserved regions. Create one region per instance, and then specify the same definition for multiple instances to assign to the same area. Not supported for reserved regions. Member exclusion Full support. No support for arbitrary logic. Use a core-only region to exclude periphery elements. Use non-rectangular regions to include more RAM or DSP columns as needed.
5.2.4.1. Logic Lock Region Assignment Examples
Assign Rectangular Logic Lock Region
Assigns a rectangular Logic Lock region to a lower right corner location of (10,10), and an upper right corner of (20,20) inclusive.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
Assign Non-Rectangular Logic Lock Region
Assigns instance with full hierarchical path "x|y|z" to non-rectangular L-shaped Logic Lock region. The software treats each set of four numbers as a new box.
set_instance_assignment –name PLACE_REGION –to x|y|z "X10 Y10 X20 Y50; X20 Y10 X50 Y20"
Assign Subordinate Logic Lock Instances
By default, the Intel® Quartus® Prime software constrains every child instance to the Logic Lock region of its parent. Any constraint to a child instance intersects with the constraint of its ancestors. For example, in the following example, all logic beneath “a|b|c|d” constrains to box (10,10), (15,15), and not (0,0), (15,15). This result occurs because the child constraint intersects with the parent constraint.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name PLACE_REGION –to a|b|c|d "X0 Y0 X15 Y15"
Assign Multiple Logic Lock Instances
By default, a Logic Lock region constraint allows logic from other instances to share the same region. These assignments place instance c and instance g in the same location. This strategy is useful if instance c and instance g are heavily interacting.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20"
Assigned Reserved Logic Lock Regions
Optionally reserve an entire Logic Lock region for one instance and any of its subordinate instances.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20" set_instance_assignment –name RESERVE_PLACE_REGION –to a|b|c ON # The following assignment causes an error. The logic in e|f|g is not # legally placeable anywhere: # set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20" # The following assignment does *not* cause an error, but is effectively # constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is reserved # for a|b|c set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X30 Y20"
5.2.5. Modify Signal Tap Logic Analyzer Files
-
Remove entity names from .stp files. The
Signal Tap Logic Analyzer allows without error, but ignores, entity names in
.stp files. Remove entity names from
.stp files for migration to
Intel®
Quartus® Prime Pro Edition:
- Click View > Node Finder to locate and remove appropriate nodes. Use Node Finder options to filter on nodes.
- Click Processing > Start > Start Analysis & Elaboration to repopulate the database and add valid node names.
-
Remove post-fit nodes.
Intel®
Quartus® Prime Pro Edition uses a different post-fit node naming scheme than
other Quartus software products.
- Remove post-fit tap node names originating from other Quartus software products.
- Click View > Node Finder to locate and remove post-fit nodes. Use Node Finder options to filter on nodes.
- Click Processing > Start Compilation to repopulate the database and add valid post-fit nodes.
-
Run an initial compilation in
Intel®
Quartus® Prime Pro Edition from the GUI. The Compiler automatically removes
Signal Tap assignments originating other Quartus software products.
Alternatively, from the command-line, run quartus_stp once on the project to remove outmoded
assignments.
Note: quartus_stp introduces no migration impact in the Intel® Quartus® Prime Pro Edition. Your scripts require no changes to quartus_stp for migration.
- Modify .sdc constraints for JTAG. Intel® Quartus® Prime Pro Edition does not support embedded .sdc constraints for JTAG signals. Modify the timing template to suit the design's JTAG driver and board.
5.2.6. Remove References to .qip Files
In Intel® Quartus® Prime Standard Edition projects, Platform Designer (Standard) generates .qip files. These files describe the parameterized IP cores to the Compiler, and appear as assignments in the project's .qsf file. However, in Intel® Quartus® Prime Pro Edition projects, the parameterized IP core description occurs in .ip files. Moreover, references to .qip files in a project's .qsf file cause synthesis errors during compilation.
5.2.7. Remove Unsupported Feature Assignments
- Incremental Compilation (partitions)—The current version of the Intel® Quartus® Prime Pro Edition software does not support Intel® Quartus® Prime Standard Edition incremental compilation. Remove all incremental compilation feature assignments from other Quartus software product .qsf files before migration.
- Intel® Quartus® Prime Standard Edition Physical synthesis assignments. Intel® Quartus® Prime Pro Edition software does not support Intel® Quartus® Prime Standard Edition Physical synthesis assignments. Remove any of the following assignments from the .qsf file or design RTL (instance assignments) before migration.
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA PHYSICAL_SYNTHESIS_COMBO_LOGIC PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION PHYSICAL_SYNTHESIS_REGISTER_RETIMING PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
5.3. Upgrade IP Cores and Platform Designer Systems
Other Quartus software products use a proprietary Verilog configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. The Intel® Quartus® Prime Pro Edition does not support this scheme. To upgrade all IP cores and Platform Designer systems in your project, click Project > Upgrade IP Components.1
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
IP and Platform Designer system generation use a proprietary Verilog HDL configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. This proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation. Resolving this issue requires writing a Verilog HDL configuration to disambiguate the instantiation, delete the duplicate entity from the project, or rename one of the conflicting entities. Intel® Quartus® Prime Pro Edition IP strategy resolves these issues. |
IP and Platform Designer system generation does not use proprietary Verilog HDL configurations. The compilation library scheme changes in the following ways:
|
5.4. Upgrade Non-Compliant Design RTL
The quartus_syn synthesis enforces stricter industry-standard HDL structures and supports the following enhancements in this release:
- Support for modules with SystemVerilog Interfaces
- Improved support for VHDL2008
- New RAM inference engine infers RAMs from GENERATE statements or array of integers
- Stricter syntax/semantics check for improved compatibility with other EDA tools
Account for these synthesis differences in existing RTL code by ensuring that your design uses standards-compliant VHDL, Verilog HDL, or SystemVerilog. The Compiler generates errors when processing non-compliant RTL. Use the guidelines in this section to modify existing RTL for compatibility with the Intel® Quartus® Prime Pro Edition synthesis.
5.4.1. Verify Verilog Compilation Unit
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
Synthesis in other Quartus software products follows the Multi-file compilation unit (MFCU) method to select compilation unit files. In MFCU, all files compile in the same compilation unit. Global definitions and directives are visible in all files. However, the default net type is reset at the start of each file. | Intel® Quartus® Prime Pro Edition synthesis follows the Single-file compilation unit (SFCU) method to select compilation unit files. In SFCU, each file is a compilation unit, file order is irrelevant, and the macro is only defined until the end of the file. |
5.4.1.1. Verilog HDL Configuration Instantiation
If your top-level entity is a Verilog HDL configuration, set the Verilog HDL configuration, rather than the module, as the top-level entity.
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
From the Example RTL, synthesis automatically finds the mid_config Verilog HDL configuration relating to the instantiated module. | From the Example RTL, synthesis does not find the mid_config Verilog HDL configuration. You must instantiate the Verilog HDL configuration directly. |
Example RTL: config mid_config; design good_lib.mid; instance mid.sub_inst use good_lib.sub; endconfig module test (input a1, output b); mid_config mid_inst ( .a1(a1), .b(b)); // in other Quartus products preceding line would have been: //mid mid_inst ( .a1(a1), .b(b)); endmodule module mid (input a1, output b); sub sub_inst (.a1(a1), .b(b)); endmodule |
5.4.2. Update Entity Auto-Discovery
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
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Always automatically searches your project directory and search path for undefined entities. | Always automatically searches your project directory and search path for undefined entities. Intel® Quartus® Prime Pro Edition synthesis performs auto-discovery earlier in the flow than other Quartus software products. This results in discovery of more syntax errors. Optionally disable auto-discovery with the following .qsf assignment: set_global_assignment -name AUTO_DISCOVER_AND_SORT OFF |
5.4.3. Ensure Distinct VHDL Namespace for Each Library
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
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For the Example RTL, the analyzer searches all libraries in an unspecified order until the analyzer finds package utilities_pack and uses items from that package. If another library, for example projectLib also contains utilities_pack, the analyzer may use this library instead of myLib.utilites_pack if found before the analyzer searches myLib. | For the Example RTL, the analyzer uses the specific utilities_pack in myLib. If utilities_pack does not exist in library myLib, the analyzer generates an error. |
Example RTL: library myLib; use myLib.utilities_pack.all; |
5.4.4. Remove Unsupported Parameter Passing
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
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From the Example RTL, synthesis overwrites the value of parameter SIZE in the instance of my_ram instantiated from entity mid-level. | From the Example RTL, synthesis generates a syntax error for
detection of parameter passing assignments in the .qsf. Specify parameters in the RTL.
The following example shows the supported top-level parameter
passing format. This example applies only to the top-level and sets
a value of 4 to parameter
N:set_parameter -name N 4 |
Example RTL: set_parameter –entity mid_level –to my_ram –name SIZE 16 |
5.4.5. Remove Unsized Constant from WYSIWYG Instantiation
Intel® Quartus® Prime Pro Edition synthesis allows use of unsized constants in .sv files for uses other than WYSIWYG instantiation. Ensure that your RTL code does not use unsized constants for WYSIWYG instantiation. For example, specify a sized literal, such as 2'b11, rather than '1.
5.4.6. Remove Non-Standard Pragmas
- vhdl(verilog)_input_version Pragma—allows change to the input version in the middle of an input file. For example, to change VHDL 1993 to VHDL 2008. For Intel® Quartus® Prime Pro Edition migration, specify the input version for each file in the .qsf.
- library Pragma—allows changes to the VHDL library into which files compile. For Intel® Quartus® Prime Pro Edition migration, specify the compilation library in the .qsf.
5.4.7. Declare Objects Before Initial Values
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
From the Example RTL, synthesis initializes the output p_prog_io1 with the value of p_progio1_reg, even though the register declaration occurs in Line 2. | From the Example RTL, synthesis generates a syntax error when you specify initial values before declaring the register. |
Example RTL: 1 output p_prog_io1 = p_prog_io1_reg; 2 reg p_prog_io1_reg; |
5.4.8. Confine SystemVerilog Features to SystemVerilog Files
set_global_assignment -name SYSTEMVERILOG_FILE <file>.v
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
From the Example RTL, synthesis interprets $clog2 in a .v file, even though the Verilog LRM does not define the $clog2 feature. Other Quartus software products allow other SystemVerilog features in .v files. | From the Example RTL, synthesis generates a syntax error for detection of any non-Verilog HDL construct in .v files. Intel® Quartus® Prime Pro Edition synthesis honors SystemVerilog features only in .sv files. |
Example RTL: localparam num_mem_locations = 1050; wire mem_addr [$clog2(num_mem_locations)-1 : 0]; |
5.4.9. Avoid Assignment Mixing in Always Blocks
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
Synthesis honors the mixed blocking and non-blocking assignments, although the Verilog Language Specification no longer supports this construct. | Synthesis generates a syntax error for detection of mixed blocking and non-blocking assignments within an ALWAYS block. |
5.4.10. Avoid Unconnected, Non-Existent Ports
To avoid syntax errors, remove all unconnected and non-existent ports for Intel® Quartus® Prime Pro Edition migration.
Other Quartus Software Products | Intel® Quartus® Prime Pro Edition |
---|---|
Synthesis allows you to instantiate and name unconnected or non-existent ports that do not exist on the module. | Synthesis generates a syntax error for detection of mixed blocking and non-blocking assignments within an ALWAYS block. |
5.4.11. Avoid Illegal Parameter Ranges
5.4.12. Update Verilog HDL and VHDL Type Mapping
5.5. Migrating to Intel Quartus Prime Pro Edition Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 | Added information about removing assignments from the qsf file that point to legacy output files. |
2018.05.07 | 18.0.0 | First release as separate chapter of Getting Started User Guide. |
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
2016.10.31 | 16.1.0 |
|
2016.05.03 | 16.0.0 |
|
2015.11.02 | 15.1.0 |
|
A. Intel Quartus Prime Pro Edition User Guides
Refer to the following user guides for comprehensive information on all phases of the Intel® Quartus® Prime Pro Edition FPGA design flow.
6. Document Archives
Intel® Quartus® Prime Version | User Guide |
---|---|
19.3 | Intel® Quartus® Prime Pro Edition User Guide: Getting Started |
18.1 | Intel® Quartus® Prime Pro Edition User Guide: Getting Started |