Introduction to High-Level Synthesis with Intel® FPGAs (IHLS2DAYPART1)
Course Description
In the class, you will learn how to use the Intel® HLS Compiler to synthesize, optimize, and verify design components for Intel FPGAs. We will first discuss the benefits of HLS, after which we will talk about features of the Intel HLS Compiler. You will learn how to use the compiler options, the generated reports, and the final generated files to integrate the IP within an Intel Quartus® Prime software project. Lastly you will learn how to effectively optimize your IP using the generated reports.At Course Completion
You will be able to:
- Use the Intel HLS Compiler to synthesize a component compatible with the Intel Quartus Prime software IP flow
- View reports to debug & optimize the component
- Co-simulate the component using an RTL simulator with a software testbench
- Integrate the HLS-generated component within an FPGA design
- Understand the various interfaces available & select the optimal one for various component types
- Effectively use various data types & math support features
- Understand how loops are pipelined
Skills Required
- Basic understanding of the C programming language
- Basic understanding of FPGAs and the Intel Quartus Prime Design Software
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
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| Location | Dates | Price | Registration |
|---|---|---|---|
| Virtual Classroom (9:00am-1:30pm Pacific Time) | 05/03/2021 - 05/04/2021 | Free | Register Now |
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