Redefining Compute Through Process and Packaging
Driving the next era of computing though transistor and packaging innovations.
Intel set the pace for computing innovation in the PC era with Moore’s Law. As data grows exponentially, so does the need for powerful chips to move, store, and process data across a distributed landscape.
Moore’s Law is as important as ever, but there’s more to it than meets the eye. Intel is powering the data-centric era with synchronized and coarchitected advances in transistors, packaging, and chip design. No other company has our fab foundation, in-house research and development capabilities, innovation pipeline, and integrated device manufacturer advantage—a unique set of complementary capabilities that will redefine what’s possible in computing.
A microprocessor may be the most complex manufactured product made by humans. Producing it takes hundreds of steps in the world’s cleanest environment, carried out by skilled experts who are meticulously trained to move atoms and molecules.
Each microprocessor is made up of billions of tiny electrical switches called transistors. As transistors grow smaller, computing devices become smarter, faster, and more efficient. But shrinking transistors is no longer enough to deliver leaps in performance. Radical design improvements are also needed.
Process Road Map Drives Progress
Intel’s process road map sets the pace for our progress over the next decade. We will continue to increase transistor density, roughly doubling the number of transistors on a unit of silicon about every two years. Between these shrinks, we’ll make process improvements every year. And every four years, Intel will release a breakthrough innovation that draws from new materials and design concepts to dramatically advance performance.
Smaller and Faster with FinFET
With our leadership in manufacturing the fin-shaped field-effect transistor (FinFET), Intel raised the 2D transistor channel into the third dimension, greatly improving control of electrons flowing through the channel. These transistors operate at a lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency. As a result, transistors are smaller, faster, and use less power than ever before.
Intel® 10nm Technology
Our 10nm process uses third-generation FinFET technology and delivers significantly better performance and lower power than our 14nm technology. The enhanced versions of our 10nm process, called 10+ and 10++, will offer additional improvements through continued refinement of FinFET transistors and interconnect design.
Intel® 7nm Technology
Our 7nm technology will be the fullest realization of the new approach outlined in our process road map, incorporating lessons learned from 14nm and 10nm. We plan to deliver 2x scaling, improvements in performance per watt, significantly less design complexity, and many waves of intranode optimizations.
As the physical interface between processor and motherboard, a chip’s packaging plays a critical role in product-level performance. Advanced packaging techniques will allow diverse computing engines to be integrated across multiple process technologies, enabling completely new approaches in system architecture.
EMIB is a cost-effective approach to connecting multiple, heterogeneous die into a single package. While other 2.5D strategies use a large silicon interposer, EMIB uses a very small bridge die with multiple routing layers. Having many embedded bridges in a single substrate provides extremely high I/O and well-controlled interconnect between multiple die.
Our Foveros packaging technology uses 3D stacking to enable logic-on-logic integration. This provides tremendous flexibility for designers to mix and match technology IP blocks with various memory and I/O elements in new device form factors. Products can be broken into smaller chiplets where I/O, SRAM, and power delivery circuits are fabricated in a base die and high-performance logic chiplets are stacked on top.
Intel’s latest packaging capabilities are unlocking new customer designs. Our Co-EMIB technology allows for the interconnection of Foveros elements with essentially the performance of a single chip. With Omni-Directional Interconnect (ODI), designers get even greater flexibility for communication among chiplets in a package.
As an integrated device manufacturer (IDM), Intel combines our powerful compute engines with leadership packaging to deliver unmatched product integration. Our complementary capabilities mean we can fully integrate our design, process, and packaging into products that are truly the best in their class. And with our portfolio of CPUs, FPGAs, accelerators, and graphics processing chips, our architects have the best flexibility to pick the right transistor for the product.
Intel’s unique processor, code-named “Lakefield,” combines a hybrid CPU with our Foveros 3D packaging technology. This architecture offers more flexibility to innovate on design, form factor, and experience. The Microsoft Surface Neo, coengineered with Intel, features Lakefield to help deliver remarkable experiences without compromising performance.
Intel is innovating across six pillars of technology development to unleash the power of data for the industry and our customers.
Intel® technologies' features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.
All information provided here is subject to change without notice.