Devido a um problema no Quartus® Prime 16.1, há clocks não restritivos relatados quando você compila os designs Arria® PCIe Hard IP Gen3 de 10 PCIe.
Isso é causado por informações ausentes em altera_pcie_express.sdc.
Para resolver este problema, faça o upgrade para a versão 17.1 do software ou adicione os seguintes comandos sdc ao final do arquivo altera_pcie_express.sdc existente.
proc skp_sdc_puts {msg {channelId stdout}} {
coloca $channelId "altera_pcie_a10_skp.sdc >> $msg"
}
proc parent_of_clock {clock_name {MAX_ATTEMPTS 100}} {
skp_sdc_puts "***
skp_sdc_puts "*** procurando a hierarquia de $clock_name *
skp_sdc_puts "***
definir tentativas 0
definir pai {}
enquanto { $attempts < $MAX_ATTEMPTS } {
skp_sdc_puts "Procurando por clocks compatíveis com \"$parent$clock_name\"..."
set matched_clock_collection [get_clocks -nowarn $parent$clock_name] ;# Experimente este curinga.
definir num_matched_clocks [get_collection_size $matched_clock_collection]
se { $num_matched_clocks == 1 } {;# Esta é a hierarquia que estamos procurando.
# Descubra o nome completo do pai.
definir pai [join [lrange [split [query_collection $matched_clock_collection] {|}] 0 {end-1}] {|}]
skp_sdc_puts "Pai encontrado: $parent"
skp_sdc_puts "***
skp_sdc_puts "*** concluir a pesquisa com o resultado: $parent * *
skp_sdc_puts "***
devolução $parent
} elseif { $num_matched_clocks > 1 } { {;# Vários clocks com o mesmo nome - isso não deve acontecer.
skp_sdc_puts "Erro: vários clocks combinam $parent$clock_name!" {stderr}
skp_sdc_puts "Erro: os clocks correspondentes são:" {stderr}
skp_sdc_puts "Erro: [query_collection $matched_clock_collection -report_format]" {stderr}
skp_sdc_puts "***
skp_sdc_puts "*** Concluir a pesquisa com erro **
skp_sdc_puts "***
Retorno
} else { ;# Subir um nível de hierarquia.
pai do apêndice {*|}
tentativas de incr
}
}
skp_sdc_puts "Erro: não foi possível encontrar o pai do $clock_name em tentativas $MAX_ATTEMPTS!"
skp_sdc_puts "***
skp_sdc_puts "*** Concluir a pesquisa com erro **
skp_sdc_puts "***
Retorno
}
derive_pll_clocks -create_base_clocks ;# derive_pll_clocks precisa ser chamado antes de parent_of_clock
derive_clock_uncertainty ;# para gerar hierarquia adequada.
definir prefixo [parent_of_clock {tx_serial_clk}]
para {set i 0} {$i != 8} {incr i} {
create_generated_clock -divide_by 1 \
-fonte "$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i]].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_2_txclk_reg" \
-nome "$prefix|rx_pcs_clk_div_by_4[$i]" \
"$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by2_1" ;# alvo
create_generated_clock -multiply_by 1 -divide_by 1 \
-fonte "$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i]].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_2_reg" \
-nome "$prefix|tx_pcs_clk_div_by_4[$i]" \
"$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by2_1" ;# target
}
remove_clock "$prefix|tx_bonding_clocks[0]"
create_generated_clock -multiply_by 1 -divide_by 10 \
-fonte "$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_b" \
-master_clock "$prefix|tx_serial_clk" \
-nome "$prefix|tx_bonding_clocks[0]" \
"$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]"
set_multicycle_path -setup -through [get_pins -compatibility_mode {*pld_rx_data*}] 0
definir rx_clkouts [lista]
para {set i 0} {$i != 8} {incr i} {
remove_clock "$prefix|g_xcvr_native_insts[$i]|rx_clk"
remove_clock "$prefix|g_xcvr_native_insts[$i]|rx_clkout"
create_generated_clock -multiply_by 1 \
-fonte "$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg" \
-master_clock "$prefix|tx_bonding_clocks[0]" \
-nome "$prefix|g_xcvr_native_insts[$i]|rx_clk" \
"$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i]].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1" ;# alvo
create_generated_clock -multiply_by 1 \
-fonte "$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg" \
-master_clock "$prefix|tx_bonding_clocks[0]" \
-nome "$prefix|g_xcvr_native_insts[$i]|rx_clkout" \
"$prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out"
set_clock_groups -exclusivo \
-grupo "$prefix|tx_bonding_clocks[0]" \
-grupo "$prefix|g_xcvr_native_insts[$i]|rx_clkout"
set_clock_groups -exclusivo \
-grupo "$prefix|tx_bonding_clocks[0]" \
-grupo "$prefix|rx_pcs_clk_div_by_4[$i]"
}