Altera recomenda não usar afi_half_clk

Este problema afeta DDR2 e DDR3, LPDDR2, QDR II e RLDRAM Produtos II.

As seguintes mensagens de aviso podem ser exibidas no TimeQuest Analisador de sincronização após executar o comando Report DDR .

Em Arria V com DDR2, DDR3, LPDDR2, QDR II, ou interfaces RLDRAM II:

Timing analysis was performed on core <corename> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

Em Arria V com LPDDR2, QDR II ou RLDRAM II Interfaces:

Core: <corename> was generated using Quartus II v12.0 for Arria V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support..

Em Cyclone V com interfaces DDR2, DDR3 ou LPDDR2:

Core: <corename> was generated using Quartus II v12.0 for Cyclone V. POF generation is not supported for this core in this release of Quartus II. You must regenerate this IP in a future version of Quartus II to obtain POF support.Timing analysis was not performed on core < corename > because the Quartus II v12.0 software contains preliminary timing models for Cyclone V devices. You must regenerate this IP in a future version of Quartus II to update the timing model and constraints.

Em Stratix V com DDR2, DDR3, QDR II ou RLDRAM Interfaces II:

Timing analysis was performed on core <corename> using Quartus II v12.0 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

A solução alternativa para este problema é não usar afi_half_clk.

Este problema não será corrigido.