Devido a um erro na arquitetura F-tile e PMA e FEC Direct PHY IP, ao configurar com uma largura PMA de largura de 16b e TX e RX de largura dupla habilitada, você pode não ver nenhuma mensagem de erro para a configuração mal selecionada na versão 22.1 do Software Quartus® Prime.
O assistente IP não reclama e permite que você gere os arquivos IP.
Durante a etapa SLG da compilação, os seguintes erros serão exibidos.
Erro (21843): Conflito 0
----------------------------------------------------------------
Erro (21843): regra: gdr_wrapper:topology_mapping_mux_rule @
Erro(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED ||
gdr.z1577a.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
Erro (21843): Regra:
gdr_virtual_channel:topo_and_stream_down_to_maib_adapter_tx_and_rx_fifo_mode_and_width_rules
@ gdr Error (21843): gdr.z1577a.topology !=
UX16E400GPTP_XX_DISABLED_XX_DISABLED ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == FALSE ||
gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src !=
E400G_STREAM15_SYS_CLK_SRC_XCVR ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode !=
E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode !=
E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use !=
E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width no interior
{E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32}
Erro (21843): regra: gdra_gdr_e400g_top::e400g_stream15_sys_clk_src_rule
@ gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_sys_clk_src ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.sys_clk_src)
!= E400G_25G_15_SYS_CLK_SRC_XCVR ||
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en)
== FALSE || gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src==
E400G_STREAM15_SYS_CLK_SRC_XCVR Error (21843): regra:
gdra_gdr_e400g_top:e400g_stream15_tx_aib_if_fifo_mode_rule @
gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en)
== FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_aib_if_fifo_mode ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_aib_if_fifo_mode)
!= E400G_25G_15_TX_AIB_IF_FIFO_MODE_REGISTER ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode ==
E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER Error (21843): regra:
gdra_gdr_e400g_top:e400g_stream15_tx_enable_rule @
gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use)
== E400G_25G_15_TX_PRIMARY_USE_DISABLED ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == TRUE Error (21843): Regra:
gdra_gdr_e400g_top:e400g_stream15_tx_excvr_if_fifo_mode_rule @
gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en)
== FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_excvr_if_fifo_mode
->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_excvr_if_fifo_mode)
!= E400G_25G_15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode ==
E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error (21843): regra:
gdra_gdr_e400g_top:e400g_stream15_tx_primary_use_rule @
gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en)
== FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use)
!= E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use ==
E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE Error (21843): regra:
gdra_gdr_e400g_top:e400g_stream15_tx_xcvr_width_rule @
gdr.z1577a.u_e400g_top Error (21843):
(gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en)
== FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_xcvr_width ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_xcvr_width)
!= E400G_25G_15_TX_XCVR_WIDTH_16 ||
gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width ==
E400G_STREAM15_TX_XCVR_WIDTH_16 Error (21843): Variáveis de entrada:
Erro (21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
Erro(21843): user.bb_f_ehip_tx[0] ->
MAC_LOOPBACK! PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx
Erro (21843): is_used == TRUE Error (21843): localização == E400G_25G_15
Erro (21843): sys_clk_src== erro de SYS_CLK_SRC_XCVR (21843):
tx_aib_if_fifo_mode == Erro de TX_AIB_IF_FIFO_MODE_REGISTER (21843): tx_en
== TRUE Error (21843): tx_excvr_if_fifo_mode ==
TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error (21843): tx_primary_use ==
TX_PRIMARY_USE_DIRECT_BUNDLE Error (21843): tx_xcvr_width ==
TX_XCVR_WIDTH_16
O problema é o gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width
Dentro
{E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32}
tx_xcvr_width == TX_XCVR_WIDTH_16 não parece ser permitida.
Para contornar esse problema, certifique-se de que apenas os modos suportados sejam gerados, conforme documentado na seção de modos suportados pelo PMA da arquitetura F-Tile e do Guia do usuário de PMA e FEC Direct PHY IP.