Devido a um problema nas versões 16.1.2 e anteriores do software Quartus Prime®, seu núcleo Arria® 10 SerialLite™ III pode exibir violações de sincronização de configuração nos caminhos entre "nó pld_10g_tx_pempty_reg" e "altera o sincronizador padrão stdsync_txpempty|din_s1" do tipo mostrado abaixo:
Do nó: seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:DUPLEX_WRAPPER.interlaken_inst|seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa: native_ilk_wrapper|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg
Nó: seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[5].stdsync_txpempty|din_s1
Clock de lançamento: seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[*]|tx_pma_clk
Clock de trava: seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[0]|tx_pma_clk
Para resolver este problema, o usuário deve modificar o arquivo ip .sdc gerado (seriallite_iii_streaming*.sdc).
As contraints originais .sdc encontradas abaixo:
set_max_skew -de [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -, para [get_keepers {*$module_name*|interlaken_native_wrapper_duplex|stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0,85
set_net_delay -de [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -para [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0,85
set_max_delay -de [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -para [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] 100
set_min_delay -de [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -para [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -100
Deve ser substituído com as seguintes contraints:
definir inst_xcvr_list [get_entity_instances twentynm_xcvr_native]
foreach each_xcvr_inst \$inst_xcvr_list {
se { [string igual a "quartus_sta" \$::TimeQuestInfo(nameofexecutable)] } { {
set_max_skew -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -, para [get_keepers {*stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0,85
}
set_net_delay -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -, para [get_keepers {*stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0,85
set_max_delay -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -, para [get_keepers {*stdsync_txpempty|din_s1}] 100
set_min_delay -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -, para [get_keepers {*stdsync_txpempty|din_s1}] -100
}
Este problema foi corrigido a partir da versão 17.0 do software Quartus Prime®.